MAX3880(1999) View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX3880
(Rev.:1999)

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

PHADJ+ PHADJ-

FIL+ FIL-

VCC

SDI+

SDI-

SLBI+

SLBI-

50Ω

AMP

AMP

50Ω

MUX

PHASE &

FREQUENCY

DETECTOR

VCC

SIS

SYNC-

SYNC+

100Ω

LVDS

TTL

D

Q

CK

LVDS

PD15+

PD15-

LOOP

FILTER

VCO

16-BIT

DEMULTIPLEXER

PD1+

LVDS

PD1-

MAX3880

CLOCK

DIVIDER

PD0+

LVDS

PD0-

LVDS

PCLK+

PCLK-

LOL

Figure 3. MAX3880 Functional Diagram

Detailed Description

The MAX3880 deserializer with clock recovery converts

2.488Gbps serial data to 16-bit-wide, 155Mbps parallel

data. The device combines a fully integrated phase-

locked loop (PLL), input amplifier, data retiming block,

16-bit demultiplexer, clock divider, and LVDS output

buffer (Figure 3). The PLL consists of a phase/frequen-

cy detector (PFD), a loop filter, and a voltage-controlled

oscillator (VCO). The MAX3880 is designed to deliver

the best combination of jitter performance and power

dissipation by using a fully differential signal architec-

ture and low-noise design techniques. The PLL recov-

ers the serial clock from the serial input data stream.

The demultiplexer generates a 16-bit-wide 155Mbps

parallel data output.

The synchronization inputs (SYNC+, SYNC-) realign the

output data word. Realignment is guaranteed to occur

within two complete PCLK cycles of the SYNC signal’s

positive transition. During synchronization, the first

incoming bit of data during that PCLK cycle is

6 _______________________________________________________________________________________

Share Link: