MAX3882A View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX3882A

2.488Gbps 1:4 Demultiplexer with Clock and Data Recovery and Limiting Amplifier

Maxim Integrated 

2.488Gbps 1:4 Demultiplexer with Clock and

Data Recovery and Limiting Amplifier

Detailed Description

The MAX3882A deserializer with clock and data recov-

ery and limiting amplifier converts 2.488Gbps serial

data to clean 4-bit-wide, 622Mbps LVDS parallel data.

The device combines a limiting amplifier with a fully inte-

grated phase-locked loop (PLL), data retiming block, 4-

bit demultiplexer, clock divider, and LVDS output buffer

(Figure 5). The PLL consists of a phase/frequency

detector (PFD), loop filter, and voltage- controlled oscil-

lator (VCO). The MAX3882A is designed to deliver the

best combination of jitter performance and power dissi-

pation by using a fully differential signal architecture

and low-noise design techniques.

The input signal to the device (SDI) passes through a

DC offset control block, which balances the input signal

to a zero crossing at 50%. The PLL recovers the serial

clock from the serial input data stream and produces

the properly aligned data and the buffered recovered

clock. The frequency of the recovered clock is divided

by four and converted to differential LVDS parallel out-

put PCLK. The demultiplexer generates 4-bit-wide

622Mbps parallel data.

VCC + 0.4V

VCC

800mV

VCC - 0.4V

VCC

VCC - 0.4V

(a) AC-COUPLED SINGLE-ENDED INPUT

800mV

VCC - 0.8V

(b) DC-COUPLED SINGLE-ENDED INPUT

Figure 1. Definition of Input Voltage Swing

VTH (mV)

5mV

+188

+170

+152

THRESHOLD-SETTING ACCURACY

(PART-TO-PART VARIATION OVER PROCESS)

5mV

1.3

1.1

VCTRL (V)

0.3

2.1

-152

-170

-188

THRESHOLD-SETTING STABILITY

(OVER TEMPERATURE AND POWER SUPPLY)

Figure 2. Relationship Between Control Voltage and Threshold

Voltage

tCK

PCLK+

tCK-Q

(PD+) - (PD-)

Figure 3. Definition of Clock-to-Q Delay

INPUT DATA

2.488Gbps PRBS 223 - 1

LOL ASSERT TIME

LOL OUTPUT

2.488Gbps PRBS 223 - 1

ACQUISITION TIME

Figure 4. LOL Assert Time and PLL Acquisition Time

Measurement

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