MAX5072ETJ View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX5072ETJ

2.2MHz, Dual-Output Buck or Boost Converter with POR and Power-Fail Output

Maxim Integrated 

2.2MHz, Dual-Output Buck or Boost

Converter with POR and Power-Fail Output

Typical Operating Characteristics (continued)

(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)

MANUAL RESET (MR)

MAX5072 toc23

MR

5V/div

RST

5V/div

VOUT1 = 3.3V

5V/div

VOUT2 = 2.5V

5V/div

100ms/div

FOUR-PHASE OPERATION

(SEE FIGURE 3)

MAX5072 toc24

SOURCE 1

(MASTER)

0V

400ns/div

SOURCE 2

0V (MASTER)

SOURCE 1

0V (SLAVE)

SOURCE 2

(SLAVE)

Pin Description

PIN

NAME

FUNCTION

1

CLKOUT Clock Output. CLKOUT is 45° phase-shifted with respect to converter 2 (SOURCE2, Figure 3). Connect

CLKOUT (master) to the SYNC of a second MAX5072 (slave) for a four-phase converter.

Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 2. Connect BST2/VDD2

2

BST2/VDD2 to an external ceramic capacitor and diode according to the Standard Application Circuit (Figure 1).

Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR 0.1µF ceramic

capacitor from BST2/VDD2 to PGND (Figure 9).

Connection to Converter 2 Internal MOSFET Drain. Buck converter operation—use the MOSFET as a

3, 4

DRAIN2 high-side switch and connect DRAIN2 to the input supply. Boost converter operation—use the MOSFET

as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 9).

5

EN2

Active-High Enable Input for Converter 2. Drive EN2 low to shut down converter 2, drive EN2 high for normal

operation. Use EN2 in conjunction with EN1 for supply sequencing. Connect to VL for always-on operation.

Feedback Input for Converter 2. Connect FB2 to a resistive divider between converter 2’s output and SGND

6

FB2 to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider

from BYPASS to regulator 2’s output (Figure 6). See the Setting the Output Voltage section.

7

COMP2 Compensation Connection for Converter 2. See the Compensation section to compensate converter 2’s

control loop.

8

PFO Dying Gasp Comparator Output. The PFO open-drain output goes low when PFI falls below the 0.78V reference.

External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the

9

SYNC switching frequency with the system clock. Each converter frequency is one half the frequency applied to

SYNC. Connect SYNC to SGND when not used.

Dying Gasp Comparator Noninverting Input. Connect a resistor-divider from the input supply to PFI. PFI

10

PFI

forces PFO low when VPFI falls below 0.78V. The PFI comparator has a 20mV (typ) hysteresis. This is an

uncommitted comparator and can be used for any protection feature such as OVP or POWER-GOOD.

_______________________________________________________________________________________ 9

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