MAX5096 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
Manufacturer
MAX5096 Datasheet PDF : 18 Pages
| |||
MAX5096/MAX5097
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Pin Description
PIN
TQFN TSSOP
1
4
2
5
3
6
4
7
5
9
6
10
7
11
8
12
9
13
10
15
11
16
12
13, 14
15, 16
—
EP
17
19, 20
1, 2, 3
8, 14, 18
EP
NAME
PGND
SGND
RESET
BP
SYNC
SS
CT
COMP
LDO/BUCK
ADJ
OUT
EN
LX
IN
N. C.
EP
FUNCTION
Power Ground. Return path for p-channel power MOSFET driver. Connect the input
capacitor return, freewheeling diode anode, and output capacitor return terminals to
PGND.
Signal Ground. Connect SGND to PGND near the input bypass capacitor return terminal.
Open-Drain, Active-Low Reset Output. RESET asserts low when OUT drops below the
reset threshold. When output rises above 92% of the programmed level, RESET becomes
high impedance after the reset timeout period. Connect a pullup resistor from RESET to
the converter output to create a logic output.
4V Internal Regulator Output. Bypass BP to SGND with a 1μF or greater ceramic
capacitor.
Synchronization Input. Connect SYNC to an external clock for synchronization. Connect
SYNC to SGND when not used.
Soft-Start Timer Input. Connect an external capacitor from SS to SGND to adjust the soft-
start timeout period (see the Soft-Start (SS) section).
Reset Timeout Period. Connect a capacitor from CT to SGND to set the reset-timeout
period (see the Power-On Reset Output RESET section).
Buck Converter (Buck Mode) Control-Loop Compensation. See the Compensation
Network section for compensation network design. LDO mode does not need external
compensation.
LDO Mode/Buck Mode Select. Drive LDO/BUCK low to select the buck mode. The buck
mode activates after 32 internal/external clock cycles. Force the LDO/BUCK high (> 2V),
to select LDO mode. The buck mode stops and LDO mode is activated with a 100μs
delay.
Regulator Output-Feedback Point. Connect ADJ to SGND for a fixed 3.3V (MAX5096A/
MAX5097A) or 5V (MAX5096B/MAX5097B). For adjustable output voltage, use an
external resistive divider to set VOUT. VADJ regulating set point is 1.237V.
Converter Output. OUT must always be connected to the regulator output. Connect at
least a 22μF low-ESR (equivalent series resistance) capacitor from OUT to PGND for
stable operation.
Enable Input. EN is internally pulled to ground. Drive EN high to turn on the regulator.
Force EN low or leave unconnected to place the device in shutdown mode.
Drain Connection of Internal p-Channel High-Side Switch
Regulator Input. Bypass IN to PGND with a parallel combination of low-ESR ceramic and
aluminum capacitor to handle the input ripple current.
No Connection. Not internally connected.
Exposed Pad. Connect externally to a large ground plane (SGND) for improved heat
dissipation. Do not use EP as an electrical ground connection.
www.maximintegrated.com
Maxim Integrated │ 9
Share Link: 