MAX6831 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX6831

Dual Ultra-Low-Voltage SOT23 µP Supervisors with Manual Reset and Watchdog Timer

Maxim Integrated 

MAX6826-MAX6831

Dual Ultra-Low-Voltage SOT23 µP Supervisors with

Manual Reset and Watchdog Timer

VCC

MAX6829/MAX6830/MAX6831

RESET TIMEOUT

DELAY GENERATOR

RESET

OR

RESET

0.63V

1.26V

VCC2

VCC

MR

WDI

WATCHDOG

TRANSITION

DETECTOR

WATCHDOG

TIMER

Figure 2. Functional Diagram of VCC2

Detailed Description

RESET/RESET Output

A microprocessor’s (µP’s) reset input starts the

µP in a known state. The MAX6826–MAX6831 µP

supervisory circuits assert a reset to prevent code-

execution errors during power-up, power-down, and

brownout conditions. Whenever a monitored voltage falls

below the reset threshold, the reset output asserts low for

RESET and high for RESET. Once all monitored voltages

exceed their reset thresholds, an internal timer keeps

the reset output asserted for the specified reset timeout

period (tRP); after this interval, reset output returns to its

original state (Figure 3).

Manual-Reset Input

Many µP-based products require manual-reset

capability, allowing the operator, a test technician, or

external logic circuitry to initiate a reset. A logic low on

MR asserts a reset. Reset remains asserted while MR is

low, and for the timeout period (140ms min) after it

returns high. MR has an internal 50kΩ pullup resistor,

so it can be left open if not used. This input can be dri-

ven with CMOS logic levels or with open-drain/collector

VCC

1V

RESET

VTH

tRP

VTH

1V

tRD

RESET

tRP

tRD

GND

Figure 3. Reset Timing Diagram

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