MAX1908 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

Manufacturer

MAX1908

Low-Cost Multichemistry Battery Chargers

Maxim Integrated 

MAX1908/MAX8724/MAX8765/MAX8765A

Low-Cost Multichemistry Battery Chargers

Pin Description

PIN

NAME

FUNCTION

1

DCIN Charging Voltage Input. Bypass DCIN with a 1µF capacitor to PGND.

2

LDO Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass with a 1µF capacitor to GND.

3

CLS Source Current-Limit Input. Voltage input for setting the current limit of the input source.

4

REF 4.096V Voltage Reference. Bypass REF with a 1µF capacitor to GND.

5

CCS Input-Current Regulation Loop-Compensation Point. Connect a 0.01µF capacitor to GND.

6

CCI Output-Current Regulation Loop-Compensation Point. Connect a 0.01µF capacitor to GND.

7

CCV Voltage Regulation Loop-Compensation Point. Connect 1kΩ in series with a 0.1µF capacitor to GND.

8

SHDN Shutdown Control Input. Drive SHDN logic low to shut down the MAX1908/MAX8724/MAX8765 MAX8765A.

Use with a thermistor to detect a hot battery and suspend charging.

Charge-Current Monitor Output. ICHG is a scaled-down replica of the charger output current. Use ICHG to

9

ICHG monitor the charging current and detect when the chip changes from constant-current mode to constant-

voltage mode. The transconductance of (CSIP - CSIN) to ICHG is 3µA/mV.

10

ACIN AC Detect Input. Input to an uncommitted comparator. ACIN can be used to detect AC-adapter presence.

11

ACOK AC Detect Output. High-voltage open-drain output is high impedance when VACIN is less than VREF/2.

12

REFIN Reference Input. Allows the ICTL and VCTL inputs to have ratiometric ranges for increased accuracy.

Output Current-Limit Set Input. ICTL input voltage range is VREFIN/32 to VREFIN. The MAX1908/MAX8724 shut

13

ICTL down if ICTL is forced below VREFIN/100 while the MAX8765/MAX8765A does not. When ICTL is equal to

LDO, the set point for CSIP - CSIN is 45mV.

14

GND Analog Ground

15

VCTL

Output Voltage-Limit Set Input. VCTL input voltage range is 0 to VREFIN. When VCTL is equal to LDO, the set

point is (4.2 x CELLS)V.

16

BATT Battery Voltage Input

17

CELLS Cell Count Input. Tri-level input for setting number of cells. GND = 2 cells, open = 3 cells, REFIN = 4 cells.

18

CSIN Output Current-Sense Negative Input

19

CSIP Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.

20

PGND Power Ground

21

DLO Low-Side Power MOSFET Driver Output. Connect to low-side nMOS gate.

22

DLOV Low-Side Driver Supply. Bypass DLOV with a 1µF capacitor to GND.

23

LX High-Side Power MOSFET Driver Power-Return Connection. Connect to the source of the high-side nMOS.

24

BST High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from LX to BST.

25

DHI High-Side Power MOSFET Driver Output. Connect to high-side nMOS gate.

26

CSSN Input Current-Sense Negative Input

27

CSSP Input Current-Sense Positive Input. Connect a current-sense resistor from CSSP to CSSN.

28

IINP

Input-Current Monitor Output. IINP is a scaled-down replica of the input current. IINP monitors the total

system current. The transconductance of (CSSP - CSSN) to IINP is 3µA/mV.

Maxim Integrated

13

Share Link: