MC68HC05EV View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MC68HC05EV

HCMOS Microcontroller Unit

Freescale Semiconductor 

Freescale Semiconductor, Inc.

General Description

Mask options

Mask options

There are two mask options on the MC68HC05E6 which are

programmed during manufacture and therefore must be specified on the

order form; COP watchdog timer enable/disable and STOP instruction

enable/disable.

LVI/options

register (LVI/OPT)

In addition, the IRQ pin can be configured to be either edge or

edge-and-level sensitive. This is done using the IRQ bit in the

LVI/options register at $0F.

There are two options on the MC68HC705E6 which are programmed

using configuration bits in the LVI/options register; COP watchdog timer

enable/disable and edge or edge-and-level sensitive IRQ triggering. The

STOP instruction is permanently enabled on the MC68HC705E6.

LVI/options (LVIOPT)

Address bit 7 bit 6 bit 5 bit 4 bit 3

$000F LVIINT LVIVAL LVIRST LVIENA

bit 2

bit 1

bit 0

State

on reset

COP IRQ 0u00 0u00

COP — Computer operating properly watchdog enable/disable

1 = COP watchdog disabled.

0 = COP watchdog enabled.

Reset clears this bit, thus the COP watchdog is enabled automatically

after reset. Because of the ‘write-once’ nature of the COP bit, it is

recommended that it be written to immediately after reset to lock the

desired state.

IRQ — Interrupt triggering sensitivity

1 = IRQ is negative edge-and-level sensitive

0 = IRQ is negative edge sensitive only

Reset clears the IRQ bit.

NOTE:

The bits in the LVIOPT register which are shaded are not relevant to this

section of the data sheet. These bits are described in Resets and

Interrupts.

3-gen

General Description

For More Information On This Product,

Go to: www.freescale.com

MC68HC05E6 — Rev. 1.0

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