Freescale Semiconductor, Inc.
Features
Table 4. Endpoint Configurations
Endpoint
Direction
Physical FIFO Size
(Bytes)
0
IN and OUT
32
1
IN or OUT
16
2
IN or OUT
16
3
IN or OUT
128
4
IN or OUT
128
Endpoint
Configuration
Control
Bulk or interrupt
Bulk or interrupt
Bulk or interrupt
Bulk or interrupt
Maximum
Packet Size
16
16
16
64
64
• Inter-IC (I2C) bus module
— Compliant with Philips I2C-bus standard (support for Standard-mode and Fast-mode)
— Support for 7-bit address
— Support for 3.0 V devices
— Multiple-master operation
— Software-programmable for 1 of 64 different serial clock frequencies
— Software-selectable acknowledge bit
— Interrupt-driven, byte-by-byte data transfer
— Arbitration-lost interrupt with automatic mode switching from master to slave
— Calling address identification interrupt
— Start and stop signal generation and detection
— Repeated START signal generation
— Acknowledge bit generation and detection
— Bus-busy detection
• In-circuit emulation module (ICEM)
— Dedicated memory space for emulator debug monitor with chip-select
— Dedicated interrupt (interrupt level 7) for in-circuit emulation
— One address-signal comparator and one control-signal comparator, with masking to support
single or multiple hardware execution breakpoints
— One breakpoint instruction insertion unit
• Operating system frequency
— Up to 66.32 MHz
• Operating voltages
— Core operates at 1.8 V
— Supply voltage: 2.7 V to 3.3 V
• Package type
— 196-pin MAP BGA
— Size: 12 mm × 12 mm
— Pitch size: 0.8 mm
MOTOROLA
Features
9
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