Freescale Semiconductor, Inc.
The Following Figures Illustrate the Measurement Reference for the MPC9600 Clock Driver Circuit
Pulse
Generator
Z = 50 W
ZO = 50 Ω
MPC9600 DUT
ZO = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 11. CCLK MPC9600 AC test reference
PCLK
PCLK
FB_IN
Differential
Pulse Generator
Z = 50 W
ZO = 50 Ω
MPC9600 DUT
ZO = 50 Ω
RT = 50 Ω
RT = 50 Ω
VTT
VTT
Figure 12. PCLK MPC9600 AC test reference
VPP
t(∅)
VCMR CCLK
B VCC
VCC 2
GND
FB_IN
t(∅)
B VCC
VCC 2
GND
B VCC
VCC 2
GND
Figure 13. Propagation delay t(∅), static phase
offset) test reference
B VCC
VCC 2
GND
tP
T0
DC = tP/T0 x 100%
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 15. Output Duty Cycle (DC)
Figure 14. Propagation delay t(∅) test reference
B VCC
VCC 2
GND
B VCC
VCC 2
GND
tSK(O)
The pin–to–pin skew is defined as the worst case difference in
propagation delay between any similar delay path within a
single device
Figure 16. Output–to–output Skew tSK(O)
TIMING SOLUTIONS
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MOTOROLA