MT28F004B3 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT28F004B3

FLASH MEMORY

Micron Technology 

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

mand is input on DQ0–DQ7, while DQ8–DQ15 are

“Don’t Care” on the MT28F400B3. The command is

latched on the rising edge of CE# (CE#-controlled) or

WE# (WE#-controlled), whichever occurs first. The con-

dition of BYTE# on the MT28F400B3 has no effect on a

command input.

MEMORY ARRAY

A WRITE to the memory array sets the desired bits to

logic 0s but cannot change a given bit to a logic 1 from a

logic 0. Setting any bits to a logic 1 requires that the entire

block be erased. To perform a WRITE, OE# must be HIGH,

CE# and WE# must be LOW, and VPP must be set to VPPH1

or VPPH2. Writing to the boot block also requires that the

RP# pin be at VHH or WP# be HIGH. A0–A17/(A18) provide

the address to be written, while the data to be written to

the array is input on the DQ pins. The data and addresses

are latched on the rising edge of CE# (CE#-controlled) or

WE# (WE#-controlled), whichever occurs first. A WRITE

must be preceded by a WRITE SETUP command. Details

on how to input data to the array are described in the

Write Sequence section.

Selectable bus sizing applies to WRITEs as it does to

READs on the MT28F400B3. When BYTE# is LOW (byte

mode), data is input on DQ0–DQ7, DQ8–DQ14 are High-

Z and DQ15 becomes the lowest order address input.

When BYTE# is HIGH (word mode), data is input on DQ0–

DQ15.

COMMAND SET

To simplify writing of the memory blocks, the

MT28F004B3 and MT28F400B3 incorporate an ISM that

controls all internal algorithms for the WRITE and ERASE

cycles. An 8-bit command set is used to control the de-

vice. Details on how to sequence commands are pro-

vided in the Command Execution section. Table 1 lists

the valid commands.

ISM STATUS REGISTER

The 8-bit ISM status register (see Table 2) is polled to

check for WRITE or ERASE completion or any related

errors. During or following a WRITE, ERASE or ERASE

SUSPEND, a READ operation outputs the status register

COMMAND

RESERVED

READ ARRAY

IDENTIFY DEVICE

READ STATUS REGISTER

CLEAR STATUS REGISTER

ERASE SETUP

ERASE CONFIRM/RESUME

WRITE SETUP

ERASE SUSPEND

Table 1

Command Set

HEX CODE DESCRIPTION

00h This command and all unlisted commands are invalid and should not

be called. These commands are reserved to allow for future feature

enhancements.

FFh

Must be issued after any other command cycle before the array can be

read. It is not necessary to issue this command after power-up or RESET.

90h Allows the device ID and manufacturer compatibility ID to be read. A0 is

used to decode between the manufacturer compatibility ID (A0 = LOW)

and device ID (A0 = HIGH).

70h Allows the status register to be read. Please refer to Table 2 for more

information on the status register bits.

50h

Clears status register bits 3-5, which cannot be cleared by the ISM.

20h The first command given in the two-cycle ERASE sequence. The ERASE is

not completed unless followed by ERASE CONFIRM.

D0h The second command given in the two-cycle ERASE sequence. Must follow

an ERASE SETUP command to be valid. Also used during an ERASE

SUSPEND to resume the ERASE.

40h or The first command given in the two-cycle WRITE sequence. The write

10h data and address are given in the following cycle to complete the WRITE.

B0h Requests a halt of the ERASE and puts the device into the erase suspend

mode. When the device is in this mode, only READ STATUS REGISTER,

READ ARRAY and ERASE RESUME commands may be executed.

4Mb Smart 3 Boot Block Flash Memory

F45_3.p65 – Rev. 3, Pub. 12/01

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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