MT28F004B3 View Datasheet(PDF) - Micron Technology

Part Name

Description

Manufacturer

MT28F004B3

FLASH MEMORY

Micron Technology 

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

contents on DQ0–DQ7 without prior command. While

the status register contents are read, the outputs are not

updated if there is a change in the ISM status unless OE#

or CE# is toggled. If the device is not in the write, erase,

erase suspend or status register read mode, READ STA-

TUS REGISTER (70h) can be issued to view the status

register contents.

All of the defined bits are set by the ISM, but only the

ISM and erase suspend status bits are reset by the ISM.

The erase, write and VPP status bits must be cleared using

CLEAR STATUS REGISTER. If the VPP status bit (SR3) is

set, the CEL does not allow further WRITE or ERASE

operations until the status register is cleared. This en-

ables the user to choose when to poll and clear the status

register. For example, the host system may perform mul-

tiple BYTE WRITE operations before checking the status

register instead of checking after each individual WRITE.

Asserting the RP# signal or powering down the device

also clears the status register.

Table 2

Status Register Bit Definitions

ISMS

ESS

ES

WS

VPPS

R

7

6

5

4

3

2–0

STATUS

BIT #

SR7

SR6

SR5

SR4

SR3

SR0-2

STATUS REGISTER BIT

DESCRIPTION

ISM STATUS (ISMS)

1 = Ready

0 = Busy

The ISMS bit displays the active status of the state machine during

WRITE or BLOCK ERASE operations. The controlling logic polls this

bit to determine when the erase and write status bits are valid.

ERASE SUSPEND STATUS (ESS)

1 = ERASE suspended

0 = ERASE in progress/completed

Issuing an ERASE SUSPEND places the ISM in the suspend mode

and sets this and the ISMS bit to “1.” The ESS bit remains “1”

until an ERASE RESUME is issued.

ERASE STATUS (ES)

1 = BLOCK ERASE error

0 = Successful BLOCK ERASE

ES is set to “1” after the maximum number of ERASE cycles is

executed by the ISM without a successful verify. ES is only cleared

by a CLEAR STATUS REGISTER command or after a RESET.

WRITE STATUS (WS)

WS is set to “1” after the maximum number of WRITE cycles is

1 = WORD/BYTE WRITE error

executed by the ISM without a successful verify. WS is only cleared

0 = Successful WORD/BYTE WRITE by a CLEAR STATUS REGISTER command or after a RESET.

VPP STATUS (VPPS)

1 = No VPP voltage detected

0 = VPP present

VPPS detects the presence of a VPP voltage. It does not monitor VPP

continuously, nor does it indicate a valid VPP voltage. The VPP pin is

sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.

VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET.

RESERVED

Reserved for future use.

4Mb Smart 3 Boot Block Flash Memory

F45_3.p65 – Rev. 3, Pub. 12/01

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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