MT4C1M16C3DJ-6 View Datasheet(PDF) - Micron Technology
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MT4C1M16C3DJ-6 Datasheet PDF : 22 Pages
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GENERAL DESCRIPTION (continued)
The MT4LC1M16C3 must be refreshed periodically
in order to retain stored data.
FAST PAGE MODE ACCESS
FAST-PAGE-MODE operations allow faster data op-
erations (READ, WRITE or READ-MODIFY-WRITE)
within a row-address-defined (A0-A9) page boundary.
The FAST-PAGE-MODE cycle is always initiated with a
row address strobed in by RAS#, followed by a column
address strobed in by CAS#. Additional columns may
be accessed by providing valid column addresses,
strobing CAS# and holding RAS# LOW, thus executing
faster memory cycles. Returning RAS# HIGH termi-
nates the FAST-PAGE-MODE operation.
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standbylevel. The chip is also preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining power
1 MEG x 16
FPM DRAM
and executing anyRAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that
all 1,024 combinations of RAS# addresses (A0-A9) are
executed at least every 16ms (128ms on the “S” ver-
sion), regardless of sequence. The CBR REFRESH cycle
will also invoke the refresh counter and controller for
row-address control.
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined
by the use of CASL# and CASH#. Enabling CASL# will
select a lower byte access (DQ0-DQ7), while enabling
CASH# will select an upper byte access (DQ0-DQ15).
Enabling both CASL# and CASH# selects a WORD
WRITE cycle.
The 1 Meg x 16 DRAM may be viewed as two 1 Meg x
8 DRAMs that have common input controls, with the
exception of the CAS# inputs. Figure 1 illustrates the
BYTE WRITE and WORD WRITE cycles. Figure 2 illus-
trates BYTE READ and WORD READ cycles.
RAS#
WORD WRITE
LOWER BYTE WRITE
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
STORED
DATA
0
0
1
0
0
0
0
0
0
X
1
1
1
1
X
0
0
0
UPPER BYTE
0
X
1
1
1
(DQ8-DQ15)
1
X
0
0
0
OF WORD
0
X
1
1
1
0
X
1
1
1
0
X
1
1
1
0
X
1
1
1
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
X
1
X
0
X
1
X
0
X
1
X
1
X
1
X
1
ADDRESS 1
Figure 1
WORD and BYTE WRITE Example
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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