PEB 20320
Introduction
– V.110/X.30 Protocol
– Automatic synchronization in receive direction, automatic generation of
the synchronization pattern in transmit direction
– E / S / X bits freely programmable in transmit direction, van be changed
during transmission; changes monitored and reported in receive direction
– Generation/detection of loss of synchronism
– Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
– Transparent Mode A
– Slot synchronous transparent transmission/reception without frame structure
– Bit-overwrite with fill/mask bits
– Flag generation, flag stuffing, flag extraction, flag generation
in the abort case with programmable flag
– Transparent Mode B
– Transparent transmission/reception in frames delimited by 00H flags
– Shared opening and closing flag
– Flag stuffing, flag detection, flag generation in the abort case
– Error detection (non octet frame content, short frame, long frame)
– Transparent Mode R
– Transparent transmission/reception with GSM 08.60 frame structure
– Automatic 0000H flag generation/detection
– Support of 40, 391/2, 401/2 octet frames
– Error detection (non octet frame content, short frame, long frame)
– Protocol Independent
– Channel inversion (data, flags, IDLE code)
– Format conventions as in CCITT Q.921 § 2.8
– Data over- and underflow detected
• Processor Interface
– ON-CHIP 64-channel DMA controller with buffer chaining capability.
– Compatible with Motorola 68020 processor family and
Intel 32-bit processor (80386).
– 32 bit data bus and 32 bit address bus (4 Gbyte RAM addressable, Motorola and
Intel non-parity) or 28 bit address bus (256 Mbyte RAM addressable, Intel parity)
– Intel parity mode with data byte parity (4 parity bits)
– Parity check for read accesses
– Parity generation for write accesses
– Interrupt-circular buffer with variable size
– Maskable interrupts for each channel
– µP interface buffer of depth 16 long words for adaptive bus occupation
User’s Manual
9
01.2000