QT301-IS View Datasheet(PDF) - Quantum Research Group
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QT301-IS Datasheet PDF : 10 Pages
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When the QT301 is done calibrating, it will release the CAL the ESD transients. In extreme cases, ESD dissipation can
pin in question to float low. A host controller can use this
be aided further by adding a resistor in series with the
feature to check when the calibration process has completed. electrode.
Calibration takes 15 acquisition burst samples to complete.
The new calibration data is stored in internal EEPROM when
the host releases the CAL pin to float low again; the chip also
begins to operate normally again at this time.
Figure 4-1 shows the control flows for calibration.
The capacitive signal on the electrode should be as stable
and noise-free as possible during the CAL intervals to ensure
accurate calibration points.
During a CAL cycle, the PWM output functions normally
using the last known good calibration data and signal value.
The PWM output will change again only when the CAL
process is complete.
Note: The CAL pins should never be driven low. Driving
either of the CAL pins low will short circuit the chip.
The charge pulse can be a minimum of 1µs and therefore the
circuit can tolerate values of series-R up to 18k in cases
where electrode Cx load is below 10pF. Extra diode
protection may be used at the electrodes but this often leads
to additional RFI problems as the diodes will rectify RF
signals into DC; this will disturb the sensing signals.
Series-R’s should be low enough to permit at least six RC
time-constants (i.e. a net RC timeconstant of 1/6 µs) to occur
during the charge pulse, where R is the added series-R and
C is the load Cx. If the series-R or Cx is too large, sensitivity
will be reduced.
Directly placing semiconductor transient protection devices
or MOV's on the sense leads is not advised; these devices
have extremely large amounts of non-linear parasitic C,
which will swamp the capacitance of the electrode and may
deliver spurious sensing results.
5 - CIRCUIT GUIDELINES
5.1 Sample Capacitor
The charge sampler capacitor (Cs) can be virtually any
plastic film or low to medium-K ceramic capacitor. The
acceptable Cs range is from 1nF to 500nF depending on the
sensitivity required; larger values of Cs demand higher
stability to ensure reliable sensing. Acceptable capacitor
types include plastic film (especially PPS film) and NP0/C0G
ceramic. X7R ceramic can also be used but this type is less
stable over temperature.
5.2 Power supply, PCB Layout
The QT301 makes use of the power supply as a reference
voltage. The acquired signal will shift slightly with changes in
VDD; fluctuations in VDD often happen when additional loads
are switched on or off such as LEDs etc.
Care should be taken when designing the power supply, as
any change in VDD will affect the PWM level.
If the power supply is shared with another electronic system,
make sure the supply is free of spikes, sags, and surges.
The supply is best locally regulated using a conventional
78L05 type regulator, or almost any 3-terminal LDO device
from 3V to 5V.
For proper operation, a 0.1µF or greater bypass capacitor
must be used between VDD and VSS; the bypass cap should
be placed very close to the device pins. The PCB should if
possible include a copper pour under and around the IC, but
not extensively under the SNS pins or lines.
5.4 RF Susceptibility
PCB layout, grounding, and the structure of the input circuitry
have a great bearing on the success of a design that can
withstand strong RF interference. The circuit is remarkably
immune to RFI provided that certain design rules are
adhered to:
1. Use SMT components to minimize lead lengths.
2. Connect electrodes to SNS1, not SNS2.
3. Use a ground plane under and around the circuit and
along the sense lines, that is as unbroken as possible
except for relief under and beside the sense lines to
reduce total Cx. Relieved rear ground planes along the
SNS lines should be ‘mended’ by bridging over them at
1cm intervals with 0.5mm ‘rungs’ like a ladder.
4. Ground planes and traces should be connected only to a
common point near the VSS pin of the IC.
5. Route sense traces away from other traces or wires that
are connected to other circuits.
6. Sense electrodes should be kept away from other
circuits and grounds which are not directly connected to
the sensor’s own circuit ground; other grounds will
appear to float at high frequencies and couple RF
currents into the sense lines.
7. Keep the Cs sampling capacitors and all series-R
components close to the IC.
8. Use a 0.1µF minimum, ceramic bypass cap very close to
the VSS/VDD supply pins.
5.3 ESD Protection
In cases where the electrode is placed behind a dielectric
panel the IC will be protected from direct static discharge.
However, even with a panel transients can still flow into the
electrodes via induction, or in extreme cases via dielectric
breakdown. Porous materials may allow a spark to tunnel
right through the material. Testing is required to reveal any
problems.
The device has diode protection on its SNS pins that absorb
most induced discharges (up to 20mA), and protect the
device. The usefulness of the internal clamping will depend
on the dielectric properties, panel thickness, and rise time of
9. Use series-R’s in the sense line of as large a value as
the circuit can tolerate without degrading sensitivity
appreciably (see Section 1.2).
10. Bypass input power to chassis ground and again at
circuit ground to reduce line-injected noise effects.
Ferrites over the power wiring may be required to
attenuate line injected noise.
Achieving RF immunity requires diligence and a good
working knowledge of grounding, shielding, and layout
techniques. Very few projects involving these devices will fail
EMC tests once properly constructed.
LQ
5
QT301 R1.04 21/09/03
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