R8A77301 View Datasheet(PDF) - Renesas Electronics
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R8A77301 Datasheet PDF : 1188 Pages
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Section 23 Serial Communication Interface with FIFO A (SCIFA) .................715
23.1 Features............................................................................................................................. 715
23.2 Input/Output Pins.............................................................................................................. 718
23.3 Register Descriptions........................................................................................................ 719
23.3.1 Receive Shift Register (SCARSR) ......................................................................... 721
23.3.2 Receive FIFO Data Register (SCAFRDR)............................................................. 721
23.3.3 Transmit Shift Register (SCATSR)........................................................................ 721
23.3.4 Transmit FIFO Data Register (SCAFTDR) ........................................................... 722
23.3.5 Serial Mode Register (SCASMR) .......................................................................... 722
23.3.6 Serial Control Register (SCASCR) ........................................................................ 726
23.3.7 FIFO Error Count Register (SCAFER) .................................................................. 730
23.3.8 Serial Status Register (SCASSR) ........................................................................... 731
23.3.9 Bit Rate Register (SCABRR)................................................................................. 738
23.3.10 FIFO Control Register (SCAFCR)......................................................................... 740
23.3.11 FIFO Data Count Register (SCAFDR) .................................................................. 743
23.3.12 Transmit Data Stop Register (SCATDSR)............................................................. 744
23.4 Operation .......................................................................................................................... 745
23.4.1 Overview................................................................................................................ 745
23.4.2 Asynchronous Mode .............................................................................................. 745
23.4.3 Serial Operation ..................................................................................................... 746
23.4.4 Synchronous Mode................................................................................................. 757
23.4.5 Serial Operation in Synchronous Mode ................................................................. 757
23.5 Interrupt Sources and DMAC ........................................................................................... 768
23.6 Usage Notes ...................................................................................................................... 769
Section 24 IrDA Interface (IrDA)......................................................................773
24.1 Features............................................................................................................................. 773
24.2 Input/Output Pins.............................................................................................................. 775
24.3 Register Descriptions........................................................................................................ 776
24.3.1 IrDA Test Register (IRIF_INT2) ........................................................................... 780
24.3.2 DMA Receive Interrupt Source Clear Register (IRIF_RINTCLR)........................ 780
24.3.3 DMA Transmit Interrupt Source Clear Register (IRIF_TINTCLR) ...................... 781
24.3.4 IrDA-SIR10 Control Register (IRIF_SIR0) ........................................................... 782
24.3.5 IrDA-SIR10 Baud Rate Error Correction Register (IRIF_SIR1) ........................... 783
24.3.6 IrDA-SIR10 Baud Rate Count Set Register (IRIF_SIR2)...................................... 784
24.3.7 IrDA-SIR10 Status Register (IRIF_SIR3) ............................................................. 785
24.3.8 Hardware Frame Processing Set Register (IRIF_SIR_FRM)................................. 785
24.3.9 EOF Value Register (IRIF_SIR_EOF)................................................................... 786
24.3.10 Flag Clear Register (IRIF_SIR_FLG).................................................................... 787
Rev. 1.00 Sep. 19, 2007 Page xxi of xlviii
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