RM7065A View Datasheet(PDF) - PMC-Sierra, Inc

Part Name

Description

Manufacturer

RM7065A

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

PMC-Sierra, Inc 

RM7065A

64-Bit MIPS RISC Microprocessor with Integrated L2 Cache

FEATURES

• Dual-issue symmetric superscalar

microprocessor

• 400 MHz max CPU frequency

• 300 MHz max CPU frequency at I-

temp (-40-85 C)

• Capable of issuing two instructions

per clock cycle

• Integrated primary and secondary

caches

• 16KB instruction, 16KB Data, and

256KB on-chip secondary

• All are 4-way set associative with

32-byte line size

• Per-line locking in primary and

secondary caches

• Fast Packet Cache™ increases

system efficiency in networking

applications

• High-performance system interface

• 1000 Mbyte per-second peak

throughput

• 125 MHz maximum frequency

multiplexed address/data bus

(SysAD)

• Supports two outstanding reads with

out-of-order return

• High-performance floating-point unit

• 800 MFLOPS maximum

• IEEE754 compliant single and

double precision floating-point

operations

• 64-bit MIPS instruction set architecture

• Data PREFETCH instruction allows

the processor to overlap cache miss

latency and instruction execution

• Single-cycle floating-point multiply-

add

• Integrated memory management unit

• Fully associative TLB

• 64/48 dual entries map 128/96

pages

• Variable page size

• Embedded application enhancements

• Specialized DSP integer Multiply-

Accumulate instructions

(MAD/MADU), and three-operand

Multiply instruction (MUL)

• I and D Test/Break-point (Watch)

registers for emulation and debug

• Performance counter for system

and software tuning and debug

• Fourteen fully prioritized vectored

interrupts-10 external, 2 internal, 2

software

PACKAGING

• Fully Static 0.18µ CMOS design with

dynamic power down logic

• 256 pin TBGA package, 27x27 mm

DEVELOPMENT TOOLS

• Operating Systems:

• Linux by MontaVista and Red Hat

• VxWorks by Wind River Systems

• Nucleus by Accelerated Technology

• Neutrino by QNX Software Systems

• Compiler Suites

• Algorithmics

• Green Hills Software

• Red Hat

BLOCK DIAGRAM

64-bit Integer Unit

Dual-Issue Superscalar

Integer Multiplier

System Control

PC Unit

64-bit FP Unit

Double/Single IEEE754

Instr. Dispatch

I-Cache

16KB, 4-way, lockable

MMU

Fully Assoc., 48 or 64 Entry

D-Cache

16KB, 4-way, lockable

PMC- 2011599 (R2)

Bus Interface Unit

64-bit

SysA /D Bus

Int Ctlr

System Cache (L2)

256KB, 4-way, lockable

NMI, INT9 – INT0

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

© Copyright PMC-Sierra, Inc. 2001

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