SC18IS600 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

SC18IS600

SPI to I2C-bus interface

Philips Electronics 

NXP Semiconductors

SC18IS600/601

SPI to I2C-bus interface

VDD

P

strong

pin latch data

input data

Fig 8. Push-pull output configuration

N

VSS

GPIO pin

glitch rejection

002aab885

6.2.2 I/O pins state register (IOState)

When read, this register returns the actual state of all programmable and

quasi-bidirectional I/O pins. When written, each register bit will be transferred to the

corresponding I/O pin programmed as output.

Table 5.

Bit

7:6

5

4

3

2

1

0

IOState - I/O pins state register (address 0x01) bit description

Symbol

Description

-

reserved

IO5

Set the logic level on the output pins.

IO4

GPIO3 (SC18IS600 only)

GPIO2

GPIO1

Write to this register:

logic 0 = set output pin to zero

logic 1 = set output pin to one

A read from this register returns states of all pins.

GPIO0

6.2.3 I2C-bus address register (I2CAdr)

The contents of the register represents the device’s own I2C-bus address. The most

significant bit corresponds to the first bit received from the I2C-bus after a START

condition. The least significant bit is not used, but should be programmed with a ‘0’.

I2CAdr is not needed for device operation, but should be configured so that its address

does not conflict with an I2C-bus device address used by the bus master.

6.2.4 I2C-bus clock rates register (I2CClk)

This register determines the I2C-bus clock frequency. Various clock rates are shown in

Table 6 for the SC18IS600. The frequency can be determined using the following formula:

I2C-bus clock frequency = 7--4-.--3-×--7---2I---28---C-×---C--1---l0--k-6- (Hz)

SC18IS600_601_3

Product data sheet

Rev. 03 — 13 December 2006

© NXP B.V. 2006. All rights reserved.

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