SC18IS600(2006) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
SC18IS600 Datasheet PDF : 28 Pages
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NXP Semiconductors
5. Pinning information
5.1 Pinning
SC18IS600/601
SPI to I2C-bus interface
GPIO0 1
CS 2
RESET 3
VSS 4
MISO 5
MOSI 6
SDA 7
SCL 8
SC18IS600IPW
16 IO5
15 WAKEUP/IO4
14 INT
13 GPIO3
12 VDD
11 SCLK
10 GPIO2
9 GPIO1
002aab713
Fig 3. SC18IS600 pin configuration for TSSOP16
GPIO0 1
CS 2
RESET 3
VSS 4
MISO 5
MOSI 6
SDA 7
SCL 8
SC18IS601IPW
16 IO5
15 WAKEUP/IO4
14 INT
13 CLKIN
12 VDD
11 SCLK
10 GPIO2
9 GPIO1
002aab714
Fig 4. SC18IS601 pin configuration for TSSOP16
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Type Description
SC18IS600 SC18IS601
GPIO0
1
1
I/O programmable I/O pin
CS
2
2
I
Chip select. When CS is LOW, the SC18IS600/601 is selected.
RESET
3
3
I
Master Reset. When active (LOW), RESET sets internal registers to
the default values, and resets the I2C-bus and SPI hardware. See
Table 3.
VSS
4
4
I
ground supply voltage
MISO
5
5
O SPI slave data output
MOSI
6
6
I
SPI slave data input
SDA
7
7
I/O I2C-bus serial data input/output
SCL
8
8
O I2C-bus serial clock output
GPIO1
9
9
I/O programmable I/O pin
GPIO2
10
10
I/O programmable I/O pin
SCLK
11
11
I
SPI clock input
VDD
12
12
I
2.4 V to 3.6 V supply voltage
GPIO3
13
-
I/O programmable I/O pin
CLKIN
-
13
I
external clock input
INT
14
14
O Interrupt. When active (LOW), INT informs the CPU that the
SC18IS600/601 has an interrupt to be serviced.
INT is reset (deactivated) either when the I2CStat register is read or as
a result of a master reset (RESET). This pin is an open-drain pin.
WAKEUP/IO4 15
15
I/O Wake up the SC18IS600/601 from the Power-down mode. Pulled LOW
by the host to wake-up from low power state. This pin can also be used
as a quasi-bidirectional I/O when not in a power-down state.
IO5
16
16
I/O quasi-bidirectional I/O pin
SC18IS600_601_3
Product data sheet
Rev. 03 — 13 December 2006
© NXP B.V. 2006. All rights reserved.
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