UPD78P368AGF-3B9 View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD78P368AGF-3B9 Datasheet PDF : 52 Pages
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mPD78P368A
(2) Non-port pins (1/2)
Pin name
RTP0-RTP3
NMI
INTP0
INTP1
INTP2
INTP3
INTP4
TI
TCUD
TIUD
TCLRUD
TO00-TO05
TO40
ANI0-ANI7
TxD0
TxD1
RxD0
RxD1
SCK
SI
SO
SB0
SB1
PWM0
PWM1
WDTO
AD0-AD7
A8-A15
ASTB
RD
WR
I/O
Function
Dual-function pin
O
Outputs a pulse in real time as triggered by a trigger signal sent from the
real-time pulse unit.
P00-P03
I
Nonmaskable interrupt request input
P20
External interrupt request input
P21
P22
P23
P24/TI
P25
I
External count clock input to timer 1
P24/INTP3
Input for the control signal to determine whether the up/down counter (timer
4) counts up or down.
P05/PWM1
External count clock input to the up/down counter (timer 4)
P06/TO40
Clear signal input to the up/down counter (timer 4)
P07
O
Pulse output from the real-time pulse unit
P80-P85
P06/TIUD
I
Analog input to the A/D converter
P70-P77
O
Serial data output from the asynchronous serial interface
P30
P35
I
Serial data input to the asynchronous serial interface
P31
P36
I/O
Serial clock I/O for the clock synchronous serial interface
P34
I
Serial data input to the clock synchronous serial interface in the 3-wire mode
P33/SB1
O
Serial data output from the clock synchronous serial interface in the 3-wire
mode
P32/SB0
I/O
Serial data I/O for the clock synchronous serial interface in the SBI mode
P32/SO
P33/SI
O
PWM signal output
P04
P05/TCUD
O
Output for the signal which indicates the watchdog timer overflowed. (A
–
nonmaskable interrupt is generated.)
I/O
Multiplexed address/data bus used when external memory is expanded
P40-P47
Address bus used when external memory is expanded
P50-P57
O
Output for the timing signal used in externally latching address information
–
output from the AD0 to AD7 and A8 to A15 pins, in order to access the
external memory
Read strobe signal output to the external memory
P90
Write strobe signal output to the external memory
P91
9
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