ADSP-2104KP-80 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-2104KP-80 Datasheet PDF : 36 Pages
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ADSP-2104/ADSP-2109
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
14 PMA BUS
14 DMA BUS
24 PMD BUS
16 DMD BUS
INSTRUCTION
REGISTER
PROGRAM
SEQUENCER
PROGRAM
MEMORY
SRAM
or ROM
DATA
MEMORY
SRAM
BOOT
ADDRESS
GENERATOR
TIMER
24
16
PMA BUS
DMA BUS
BUS
EXCHANGE
PMD BUS
DMD BUS
14
MUX
EXTERNAL
ADDRESS
BUS
24
MUX
EXTERNAL
DATA
BUS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
INPUT REGS
SHIFTER
OUTPUT REGS
16
R Bus
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
5
Figure 1. ADSP-2104/ADSP-2109 Block Diagram
ARCHITECTURE OVERVIEW
Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. The processor contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data directly
and have provisions to support multiprecision computations.
The ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. The MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead—no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. The processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
One bus grant execution mode (GO Mode) allows the ADSP-
2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.
REV. 0
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