AD7664 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7664 Datasheet PDF : 24 Pages
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AD7664
Parameter
Conditions
Min
Typ
Max
TEMPERATURE RANGE8
Specified Performance
TMIN to TMAX
–40
+85
NOTES
1LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4In Normal Mode.
5Tested in Parallel Reading Mode.
6In Impulse Mode.
7With all digital inputs forced to OVDD or OGND, respectively.
8Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS (–40؇C to +85؇C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
REFER TO FIGURES 11 AND 12
Convert Pulse Width
Time between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
t1
5
t2
1.75/2/2.25
t3
t4
Note 1
25
1.5/1.75/2
t5
2
t6
10
t7
1.5/1.75/2
t8
250
t9
10
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
t11
45
t12
t13
5
1.5/1.75/2
40
15
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
t14
CS LOW to Internal SCLK Valid Delay2
t15
CS LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay
t17
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
t18
Internal SCLK Period
t19
Internal SCLK HIGH (INVSCLK Low)3
t20
Internal SCLK LOW (INVSCLK Low)3
t21
SDOUT Valid Setup Time
t22
SDOUT Valid Hold Time
t23
SCLK Last Edge to SYNC Delay
t24
CS HIGH to SYNC HI-Z
t25
CS HIGH to Internal SCLK HI-Z
t26
CS HIGH to SDOUT HI-Z
t27
BUSY HIGH in Master Serial Read after Convert
t28
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to SYNC Asserted Delay
t29
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t30
10
10
10
25/275/525
4
40
75
30
9.5
4.5
3
3
10
10
10
2.75/3/3.25
1/1.25/1.5
50
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)2
External SCLK Setup Time
t31
5
External SCLK Active Edge to SDOUT Delay
t32
3
16
SDIN Setup Time
t33
5
SDIN Hold Time
t34
5
External SCLK Period
t35
25
External SCLK HIGH
External SCLK LOW
t36
10
t37
10
NOTES
1In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
REV. E
–3–
Unit
°C
Unit
ns
µs
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
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