SST25VF010 View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST25VF010

1 Mbit SPI Serial Flash

Silicon Storage Technology 

Data Sheet

PRODUCT IDENTIFICATION

TABLE 2: PRODUCT IDENTIFICATION

Manufacturer’s ID

Device ID

SST25VF010

Address

00000H

00001H

Data

BFH

49H

T2.0 1233

MEMORY ORGANIZATION

The SST25VF010 SuperFlash memory array is organized

in 4 KByte sectors with 32 KByte overlay blocks.

1 Mbit SPI Serial Flash

SST25VF010

DEVICE OPERATION

The SST25VF010 is accessed through the SPI (Serial

Peripheral Interface) bus compatible protocol. The SPI bus

consist of four control lines; Chip Enable (CE#) is used to

select the device, and data is accessed through the Serial

Data Input (SI), Serial Data Output (SO), and Serial Clock

(SCK).

The SST25VF010 supports both Mode 0 (0,0) and Mode 3

(1,1) of SPI bus operations. The difference between the

two modes, as shown in Figure 2, is the state of the SCK

signal when the bus master is in Stand-by mode and no

data is being transferred. The SCK signal is low for Mode 0

and SCK signal is high for Mode 3. For both modes, the

Serial Data In (SI) is sampled at the rising edge of the SCK

clock signal and the Serial Data Output (SO) is driven after

the falling edge of the SCK clock signal.

©2003 Silicon Storage Technology, Inc.

4

S71233-01-000

8/03

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