SST25VF080B View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

Manufacturer

SST25VF080B

8 Mbit SPI Serial Flash

Silicon Storage Technology 

A Microchip Technology Company

8 Mbit SPI Serial Flash

SST25VF080B

Hold Operation

Data Sheet

The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without reset-

ting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#

mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The

HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.

If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device

enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the

HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode

when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.

Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be VIL or VIH.

If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as

HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device,

HOLD# must be driven active high, and CE# must be driven active low. See Figure 24 for Hold timing.

SCK

HOLD#

Active

Hold

Figure 4: Hold Condition Waveform

Active

Hold

Active

1296 HoldCond.0

Write Protection

SST25VF080B provides software Write protection. The Write Protect pin (WP#) enables or disables

the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL)

in the status register provide Write protection to the memory array and the status register. See Table 4

for the Block-Protection description.

Write Protect Pin (WP#)

The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.

When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by

the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled.

Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction

WP#

L

L

H

BPL

1

0

X

Execute WRSR Instruction

Not Allowed

Allowed

Allowed

T2.0 1296

©2011 Silicon Storage Technology, Inc.

6

S71296-05-000

02/11

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