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SST25VF080B View Datasheet(PDF) - Silicon Storage Technology

Part Name
Description
Manufacturer
SST25VF080B
SST
Silicon Storage Technology SST
SST25VF080B Datasheet PDF : 36 Pages
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A Microchip Technology Company
8 Mbit SPI Serial Flash
SST25VF080B
Data Sheet
Status Register
The software status register provides status on whether the flash memory array is available for any
Read or Write operation, whether the device is Write enabled, and the state of the Memory Write pro-
tection. During an internal Erase or Program operation, the status register may be read only to deter-
mine the completion of an operation in progress. Table 3 describes the function of each bit in the
software status register.
Table 3: Software Status Register
Bit Name
0 BUSY
1 WEL
2 BP0
3 BP1
4 BP2
5 BP3
6 AAI
7 BPL
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 4)
Indicate current level of block write protection (See Table 4)
Indicate current level of block write protection (See Table 4)
Indicate current level of block write protection (See Table 4)
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
Default at
Power-up
0
0
1
1
1
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R
R/W
T3.0 1296
Busy
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is completed or reached its highest unpro-
tected memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instructions
©2011 Silicon Storage Technology, Inc.
7
S71296-05-000
02/11

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