ST10F163 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST10F163 Datasheet PDF : 58 Pages
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ST10F163
Table 1 : Pin definitions and functions (continued)
Symbol
PORT1:
P1L.0-P1L.7
P1H.0-P1H.7
RSTIN
RSTOUT
NMI
P6.0-P6.7
P2.8 –P2.15
VPP
VDD
VSS
Pin Input (I)
Number( Output
TQFP )
(O)
Function
59-66
67, 68
71-76
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input
or output via direction bits. For a pin configured as input, the output driver is put
into high-impedance state. PORT1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a demultiplexed bus
mode to a multiplexed bus mode.
79
I
Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a
specified duration while the oscillator is running resets the device. An internal
pullup resistor permits power-on reset using only a capacitor connected to
VSS.
80
O Internal Reset Indication Output. This pin is set to a low level when the part is
executing either a hardware-, a software- or a watchdog timer reset. RSTOUT
remains low until the EINIT (end of initialization) instruction is executed.
81
I
Non-Maskable Interrupt Input. A high to low transition at this pin causes the
CPU to vector to the NMI trap routine. When the PWRDN (power down) instruc-
tion is executed, the NMI pin must be low in order to force the ST10R65 to go
into power down mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
82-89
I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direc-
tion bits. For a pin configured as input, the output driver is put into high-imped-
ance state. Port 6 outputs can be configured as push/pull or open drain drivers.
The following Port 6 pins have alternate functions:
82
O P6.0
CS0
Chip Select 0 Output
...
... ...
...
...
86
O P6.4
CS4
Chip Select 4 Output
87
I
P6.5
HOLD
External Master Hold Request Input
(Master mode: O, Slave mode: I)
88
I/O P6.6
HLDA
Hold Acknowledge Output
89
O P6.7
BREQ
Bus Request Output
90 - 97
I/O Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or
output via direction bits. For a pin configured as input, the output driver is put
into high-impedance state. Port 2 outputs can be configured as push/pull or
open drain drivers.
The following Port 2 pins also serve for alternate functions:
90
I
P2.8
EX0IN
Fast External Interrupt 0 Input
...
... ...
...
...
97
I
P2.15
EX7IN
Fast External Interrupt 7 Input
40
-
Flash programming voltage. This pin accepts the programming voltage for the
on-chip flash EPROM. In the ST10F163, bit 4of SYSCON register serves as an
enable/disable control for the OWD.
7, 28, 38,
49, 69,
78
-
Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
> 2.5 V during power down mode
4, 27, 39,
50, 70,
77
-
Digital Ground.
8/58
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