ST10F163
III - FUNCTIONAL DESCRIPTION
The architecture of the ST10F163 combines the
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The fol-
Figure 3 : Block diagram
lowing block diagram gives an overview of the dif-
ferent on-chip components and of the advanced,
high bandwidth internal bus structure.
32
Internal
FLASH
Memory
CPU-Core
16
16
Internal
RAM
16
Watchdog
16
PEC
Interrupt Controller
16
PLL
OSC.
16
SSP
GPT1 ASC
T2
(usart)
Ext.
16
Bus
Con-
troller
T3
T4
GPT2
T5
8
BRG
T6
BRG
Port 6
Port 5
Port 3
8
6
15
Port 2
8
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