ST16C1450(2005) View Datasheet(PDF) - Exar Corporation
Part Name
Description
Manufacturer
ST16C1450 Datasheet PDF : 28 Pages
| |||
ST16C1450
2.97V TO 5.5V UART
xr
REV. 4.2.1
NAME
28-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
DSR# 26
39
I Data Set Ready input or general purpose input (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, connect
it to VCC.
CD# 27
40
I Carrier Detect input or general purpose input (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, connect
it to VCC.
RI#
17
21
I Ring Indicator input or general purpose input (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, connect
it to VCC.
ANCILLARY SIGNALS
XTAL1 12
15
I Crystal or external clock input. See Figure 3 for typical oscillator connections.
XTAL2 13
16
O Crystal or buffered clock output. See Figure 3 for typical oscillator connections.
RESET 24
33
I Reset Input (active high). When it is asserted, the UART configuration registers are
reset to default values, see Table 6.
RST
-
22
O Reset Output (active high). This output is only available on the ST16C1451. When
IER bit-5 is a logic 0, RST will follow the logical state of the RESET pin. When IER bit-
5 is a logic 1, the user may send software (soft) resets via MCR bit-2. Soft resets from
MCR bit-2 are “ORed” with the state of the RESET pin.
VCC 28
41 Pwr Power supply input of 2.97 to 5.5V.
GND 15
19 Pwr Power supply common ground.
N.C.
-
1, 2, - Not connected.
10-14,
18,
24-26,
29,
35-38,
42, 44,
48
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
1.0 PRODUCT DESCRIPTION
The ST16C1450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-
parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required in digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The 1450 is capable of
operation up to 1.5 Mbps with a 24 MHz crystal or external clock input with a 16X sampling clock (at VCC =
5.0V). With a crystal of 14.7456 MHz and through a software option, the user can select data rates up to 921.6
Kbps.
4
Share Link: 