STK25C48 View Datasheet(PDF) - Simtek Corporation
Part Name
Description
Manufacturer
STK25C48 Datasheet PDF : 10 Pages
| |||
STK25C48
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
tELQV
2
tAVAVf
3
tAVQVg
tACS
tRC
tAA
4
tGLQV
tOE
5
tAXQXg
tOH
6
tELQX
tLZ
7
tEHQZh
tHZ
8
tGLQX
tOLZ
9
tGHQZh
tOHZ
10
tELICCHe
tPA
11
tEHICCLd, e
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
(VCC = 5.0V ± 10%)
STK25C48-25 STK25C48-35 STK25C48-45
UNITS
MIN MAX MIN MAX MIN MAX
25
35
45
ns
25
35
45
ns
25
35
45
ns
10
15
20
ns
5
5
5
ns
5
5
5
ns
10
13
15
ns
0
0
0
ns
10
13
15
ns
0
0
0
ns
25
35
45
ns
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledf
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
11
tEHICCL
7
tEHQZ
G
DQ (DATA OUT)
ICC
8
tGLQX
4
tGLQV
10
tELICCH
STANDBY
ACTIVE
9
tGHQZ
DATA VALID
March 2006
3 Document Control # ML0005 rev 0.2
Share Link: 