TDA9141 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

TDA9141

PAL / NTSC / SECAM decoder/sync processor

Philips Electronics 

Philips Semiconductors

PAL/NTSC/SECAM decoder/sync

processor

Product specification

TDA9141

When the controller is in the

NEAR_NORM state it will move to the

COUNT state if it detects the vertical

sync pulse within the NEAR_NORM

window (i.e. 622 < LC < 628). If no

vertical sync pulse is detected, the

controller will move back to the

COUNT state when the line counter

reaches LC = 628. The line counter

will then be reset.

When the controller is in the

NO_NORM state it will move to the

COUNT state when it detects a

vertical sync pulse and reset the line

counter. If a vertical sync pulse is not

detected before LC = 722 (if the

Phase 1 loop is locked in forced

mode) it will move to the COUNT

state and reset the line counter. If the

Phase 1 loop is not locked the

controller will move back to the

COUNT state when LC = 628.

The forced mode option keeps the

controller in either the left-hand side

(60 Hz) or the right-hand side (50 Hz)

of the state diagram.

Figure 6 illustrates the state diagram

of the norm counter which is an

up/down counter that counts up if it

finds a vertical sync pulse within the

selected window. In the

NEAR_NORM and NORM states the

first correct vertical sync pulse after

one or more incorrect vertical sync

pulses is processed as an incorrect

pulse. This procedure prevents the

system from staying in the

NEAR_NORM or NORM state if the

vertical sync pulse is correct in the

first field and incorrect in the second

field. If no vertical sync pulse is found

in the selected window this will always

result in a down pulse for the norm

counter.

Output port and input/output port

Two stand-alone ports are available

for external use. These ports are

I2C-bus controlled, the output port by

bus bit OPB and the input/output port

by bus bit OPA. Bus bit OPA is an

open-drain output, to enable input

port functioning. The pin status is

read out by bus via output bit IP.

Sandcastle

Figure 7 illustrates the timing of the

acquisition sandcastle (ASC) and the

VA pulse with respect to the input

signal. The sandcastle signal is in

accordance with the 2-level 5 V

sandcastle format. An external

vertical guard current can overrule the

sink current to enable blanking

purposes.

December 1992

8

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