QT140 View Datasheet(PDF) - Quantum Research Group
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QT140 Datasheet PDF : 14 Pages
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Unused channels should not have sense traces or
electrodes connected to them.
3.6 ESD PROTECTION
In cases where the electrode is placed behind a dielectric
panel, the IC will be protected from direct static discharge.
However even with a panel, transients can still flow into the
electrodes via induction, or in extreme cases via dielectric
breakdown. Porous materials may allow a spark to tunnel
right through the material. Testing is required to reveal any
problems. The device does have diode protection on its SNS
pins which absorb and protect the device from most induced
discharges, up to 20mA; the usefulness of the internal
clamping will depending on the dielectric properties, panel
thickness, and rise time of the ESD transients.
In extreme cases ESD dissipation can be aided further by
adding 1K series resistors in series with the electrodes as
shown in Figures 1-6 through 1-8. Because the charge time
is 1.2µs, the circuit can tolerate large values of series-R, up
to 20k ohms in cases where electrode Cx load is below
10pF. Extra diode protection at the electrodes can also be
used, but this often leads to additional RFI problems as the
diodes will rectify RF signals into DC which will disturb the
signals.
If the series-R is too large, sensitivity will drop off.
Directly placing semiconductor transient protection devices
or MOV's on the sense leads is not advised; these devices
have extremely large amounts of nonlinear parasitic C which
will swamp the capacitance of the electrode and cause
strange sensing problems.
Series-R’s should be low enough to permit at least 6 RC
time-constants to occur during the charge and transfer
phases, where R is the added series-R and C is the load Cx.
If the device is connected to an external control circuit via a
cable or long twisted pair, it is possible for ground-bounce to
cause damage to the Out pins and/or interfere with key
sensing. Noise current injection into the power supply is best
dealt with by shunting the noise aside to chassis ground with
capacitors, and further limited using resistors or ferrites.
3.7 RFI PROTECTION
PCB layout, grounding, and the structure of the input circuitry
have a great bearing on the success of a design that can
withstand strong RF interference.
The circuit is remarkably immune to RFI provided that certain
design rules are adhered to:
1. Use SMT components to minimize lead lengths.
2. Connect electrodes to SNSnA, not SNSnB pins.
3. Use a ground plane under and around the circuit and
along the sense lines, that is as unbroken as possible
except for relief under and beside the sense lines to
reduce total Cx. Relieved rear ground planes along the
SNS lines should be ‘mended’ by bridging over them at
1cm intervals with 0.5mm ‘rungs’ like a ladder.
4. Ground planes and traces should be connected only to a
common point near the Vss pins of the IC.
5. Route sense traces away from other traces or wires that
are connected to other circuits.
6. Sense electrodes should be kept away from other
circuits and grounds which are not directly connected to
the sensor’s own circuit ground; other grounds will
appear to float at high frequencies and couple RF
currents into the sense lines.
7. Keep the Cs sampling capacitors and all series-R
components close to the IC.
8. Use a 0.1µF minimum ceramic bypass cap very close to
the Vss / Vdd supply pins.
9. Use series-R’s in the sense lines, of as large a value as
the circuit can tolerate without degrading sensitivity
appreciably.
10.Bypass input power to chassis ground and again at
circuit ground to reduce line-injected noise effects.
Ferrites over the power wiring may be required to
attenuate line injected noise.
Achieving RF immunity requires diligence and a good
working knowledge of grounding, shielding, and layout
techniques. Very few projects involving these devices will fail
EMC tests once properly constructed.
lQ
9
QT140/150 1.01/1102
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