TRC101 View Datasheet(PDF) - RF Monolithics, Inc
Part Name
Description
Manufacturer
TRC101 Datasheet PDF : 33 Pages
| |||
Configuration Register [POR=8008h]
Bit Bit Bit Bit Bit Bit Bit Bit Bit
15 14 13 12 11 10 9 8
7
Bit Bit
6
5
Bit Bit Bit Bit Bit
4
3
2
1
0
1 0 0 0 0 0 0 0 DATEN FIFEN BAND1 BAND0 CAP3 CAP2 CAP1 CAP0
The configuration register sets up the following:
• Internal Data Register
• Internal FIFO
• Frequency Band in use
• Crystal Load capacitance
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the configuration register.
Bit [7] – Data Register Enable: This bit enables the internal data register when set. If the internal data
register is used, the FSK pin (6) must be connected to GND.
Bit [6] – FIFO Enable: This bit enables the internal data FIFO when set. The FIFO is used to store data
during receive. If the FIFO is disabled by clearing this bit, pin 6 (Data) and pin 7 (Recovered Clock) are
used to receive data. See Data Buffer Setup Register section for details on the FIFO configuration.
Bit [5..4] – Band Select: These bits set the frequency band to be used. There are four (4) bands that are
supported. See Table 3 below for Band configuration.
TABLE 3.
Frequency Band BAND1
315
0
433
0
868
1
916
1
BAND0
0
1
0
1
Bit [3..0] – Load Capacitance Select: These bits set the load capacitance for the crystal reference. The
internal load capacitance can be varied from 8.5pF to 16pF in 0.5pF steps to accommodate a wide range
of crystal vendors as well as adjust the reference frequency and compensate for stray capacitance that
may be introduced due to PCB layout. See Table 4 below for load capacitance configuration.
TABLE 4.
CAP3 CAP2 CAP1 CAP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
……
1
1
1
0
1
1
1
1
Crystal Load
Capacitance
8.5
9
9.5
10
……
15.5
16
13
Share Link: 