UPD16661A View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD16661A Datasheet PDF : 36 Pages
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µPD16661A
1. BLOCK FUNCTIONS
(1) Address management circuit
The address management circuit converts the addresses transferred from the system via A0 to A16 into
addresses compatible with the memory map of the on-chip RAM.
This function can be used to address up to VGA size (480 × 640 dots) with 8 of these LSIs, thus making it
possible to configure a liquid-crystal display system without difficulty.
(2) Arbiter
The arbiter adjusts the contention between the RAM access from the system and the RAM read on the liquid-
crystal drive side.
(3) RAM
Static RAM (single port) of 160 × 240 × 2 bits
(4) Data bus control
The data bus controls the data transfer directions by means of Read/Write from the system.
The mode can be switched from 8 bits to 16 bits by the BMODE pin, and the relation between the display data
and the gray scale can be switched by the GMODE pin.
(5) Frame thinning-out control
The frame thinning-out control indicates the four gray scales with three thinning-out frames. The thinning-out
method can be changed in units of 9 pixels (3 columns × 3 lines).
(6) Internal timing generation
The internal timing to each block is generated from the /FRM and STB signals.
(7) CR oscillator
In master mode, this oscillator generates the clock that is the reference for the frame frequency. The frame
frequency is one 484th (1/484) of this oscillation. For example, if the frame frequency is 80 Hz, an oscillation
frequency of 38.72 kHz is necessary. As the CR has a built-in capacitance, adjust the required oscillation
frequency with an externally attached resistor.
In slave mode, oscillation is stopped.
(8) Liquid-crystal timing generation
In master mode, /FRM (the frame signal) and STB (the column drive signal strobe) are generated.
(9) FRC control
This circuit realizes the four gray-scale displays.
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