V54C3256164VBUC View Datasheet(PDF) - Mosel Vitelic, Corp

Part Name

Description

Manufacturer

V54C3256164VBUC

V54C3256164VBUC/T LOW POWER 256Mbit SDRAM 3.3 VOLT, 54-BALL SOC BGA 54-PIN TSOPII 16M X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

V54C3256164VBUC/T

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

WRITE A

READ B

NOP

NOP

NOP

NOP

NOP

NOP

CAS latency = 2

tCK2, I/O’s

CAS latency = 3

tCK3, I/O’s

DIN A0

don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

DIN A0

don’t care don’t care

DOUT B0 DOUT B1 DOUT B2 DOUT B3

Input data must be removed from the I/O’s at least one clock

cycle before the Read dataAPpears on the outputs to avoid

data contention.

7. Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND

BANK A

ACTIVE

NOP

CAS latency = 2

I/O’s

CAS latency = 3

I/O’s

NOP

WRITE A

Auto-Precharge

NOP

DIN A0

DIN A1

DIN A0

DIN A1

NOP

t WR

t WR

NOP

NOP

tRP

*

tRP

* Begin Autoprecharge

Bank can be reactivated after trp

NOP

V54C3256164VBUC/T Rev. 1.1 February 2003

20

Share Link: