VSC7216-01 View Datasheet(PDF) - Vitesse Semiconductor

Part Name

Description

Manufacturer

VSC7216-01

Multi-Gigabit Interconnect Chip

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7216-01

Multi-Gigabit Interconnect Chip

There are four distinct modes of operation defined in Table 7. The first row disables both word alignment

and rate matching. (The fourth and fifth row configurations function identically to the first row.) The second

row configures the channels to operate independently with rate matching. Word alignment is disabled, and

IDLEs will be dropped/duplicated independently in each channel as required. The third row configures the part

to perform word alignment and rate matching. The receive channels will be aligned per the device driving

WSO, and IDLE words will be dropped/duplicated across the aligned channels as required. The last row

configures the part to perform word alignment and disables rate matching. This mode of operation is

appropriate for a frequency-locked application where it desired to align the receive channels without altering

the received data streams.

Using Multiple VSC7216-01s in Parallel

Multiple VSC7216-01s can be used in parallel to form wider bus widths. In order for word alignment to

function correctly across multiple devices, each transmit channel’s input data must be transmitted on a common

clock, and each receive channel’s output data must also be aligned to a common word clock. This requires that

all transmitting devices use either the same or identical REFCLKs, and that TMODE(2:0)=000 (inputs timed to

REFCLK) or TMODE(2:0)=1X0 (inputs timed to TBCA). If inputs are timed to TBCA, then all transmitting

devices must use either the same or identical TBCAs. Since all receive channels must use a common word

clock, the receiving devices must also use the same or identical REFCLKs and it must be selected as the word

clock for all receive channels (RMODE(1:0)=0X).

If the transmitting devices’ REFCLKs are not frequency-locked to the receiving devices’ REFCLKs,

IDLEs will have to be added to or dropped from all the channels at the same time. In order to implement this,

one VSC7216-01 is arbitrarily chosen as the “Master” and its WSO output is driven to the WSI inputs of all the

receiving VSC7216-01s, including itself. WSO is asserted prior to the VSC7216-01 adding/dropping IDLEs so

all the VSC7216-01s will operate simultaneously. WSO uses a simple 3-bit serial protocol, synchronous to the

Master channel’s word clock for indicating the required synchronization action to other VSC7216-01s. A steady

LOW level indicates no action is required. ‘101’ indicates that Master Channel A has seen a Word Sync Event.

The relative timing relationship between receiving a Word Sync Event (on all channels together) and seeing

‘101’ on the WSI input in the other channels allows these channels to word-synchronize with Master Channel

A. ‘110’ indicates that the next IDLE encountered in the receive data stream should be deleted. ‘111’ indicates

that an IDLE should be inserted after the next IDLE encountered in the receive data stream. Note that the

arbitrarily chosen Master Channel A must be an active channel.

Decoder Bypass Mode

If ENDEC is LOW, the 8B/10B decoder is bypassed and a 10-bit received character Rn(9:0) is output from

each receive channel. The KCHn output becomes Rn8, and ERRn becomes Rn9. Character alignment is

handled differently in this mode of operation. As mentioned in the “Encoder Bypass Mode” section, the

KCHAR input becomes ENCDET which enables Comma detection and re-synchronization when HIGH, and

disables re-synchronization when LOW. Only the ‘0011111xxx’ version of the “Comma” pattern is recognized

when ENDEC is LOW. The IDLEn output becomes COMDET (Comma Detect) which signals detection of the

‘0011111xxx’ Comma pattern in the current 10-bit output character when HIGH. This mode of operation is

equivalent to a 10-bit interface commonly found in serializer/deserializers for the Fibre Channel (VSC7125)

and Gigabit Ethernet markets (VSC7135).

G52352-0, Rev 3.2

05/05/01

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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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