WED3DL644V8BC View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
Manufacturer
WED3DL644V8BC Datasheet PDF : 28 Pages
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White Electronic Designs
WED3DL644V
SDRAM AC CHARACTERISTICS
Parameter
Clock Cycle Time1
Clock to valid Output delay1,2
Output Data Hold Time2
Clock HIGH Pulse Width3
Clock LOW Pulse Width3
Input Setup Time3
Input Hold Time3
CK to Output Low-Z2
CK to Output High-Z
Row Active to Row Active Delay4
RAS# to CAS# Delay4
Row Precharge Time4
Row Active Time4
Row Cycle Time - Operation4
Row Cycle Time - Auto Refresh4,8
Last Data in to New Column Address Delay5
Last Data in to Row Precharge5
Last Data in to Burst Stop5
Column Address to Column Address Delay6
Data Out to High Impedance from Precharge
CL = 3
CL = 2
CL3
CL2
Symbol
tCC
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
tRRD
tRCD
tRP
tRAS
tRC
tRFC
tCDL
tRDL
tBDL
tCCD
tROH
tROH
133MHZ
Min Max
7 1000
7.5 1000
5.4
2
2.5
2.5
2
1
1.0
5.4
14
15
15
37 120,000
60
66
1
2
1
1.0
3
2
125MHZ
Min Max
8 1000
10 1000
6
2
2.75
2.75
2
1
1
6
20
20
20
50 120,000
70
70
1
2
1
1.0
3
2
100MHZ
Min Max
10 1000
12 1000
7
2
3
3
2
1
1.5
7
20
20
20
50 120,000
80
80
1
2
1
1.5
3
2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
NOTES:
1. Parameters depend on programmed CAS# latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up
to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit
August 2005
Rev. 6
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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