WED3DL644V8BC View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
Manufacturer
WED3DL644V8BC Datasheet PDF : 28 Pages
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White Electronic Designs
WED3DL644V
COMMAND TRUTH TABLE
Function
Register
Mode Register Set
Refresh
Auto Refresh (CBR)
Entry Self Refresh
Precharge
Single Bank Precharge
Precharge all Banks
Bank Activate
Write
Write with Auto Precharge
Read
Read with Auto Precharge
Burst Termination
No Operation
Device Deselect
Clock Suspend/Standby Mode
Data Write/Output Disable
Data Mask/Output Disable
Entry
Power Down Mode
Exit
CKE
Previous Current CE# RAS# CAS# WE# DQM
Cycle Cycle
H
X
LL
L
L
X
H
H
LL
LHX
H
L
LL
LHX
H
X
L
L
H
L
X
H
X
L
L
H
L
X
H
X
L
L
H
H
X
H
X
L
H
L
L
X
H
X
L
H
L
L
X
H
X
L
H
L
L
X
H
X
L
H
L
H
X
H
X
L
H
H
L
X
H
X
L
H
H
H
X
H
X
HX
XXX
L
X
XX
XXX
H
X
XX
XXL
H
X
XX
XXH
X
L
HX
XXX
X
H
HX
XXX
BA0-1
A10/AP
A9-0
A11 Notes
OP CODE
X
X
X
X
X
X
BA
L
X
X
H
X
BA
Row Address
BA
L Column
BA
H Column
BA
L Column
BA
H Column
X
X
X
2
X
X
X
X
X
X
X
X
X
3
X
X
X
4
X
X
X
4
X
X
X
5
X
X
X
5
NOTES:
1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.
2. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
3. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock
delay is required for mode entry and exit.
4. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is
prohibited (zero clock latency).
5. All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device can’t
remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
August 2005
Rev. 6
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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