WED3EG7218S403JD3 View Datasheet(PDF) - White Electronic Designs Corporation
Part Name
Description
Manufacturer
WED3EG7218S403JD3 Datasheet PDF : 12 Pages
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White Electronic Designs
WED3EG7218S-JD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262/265
202
Parameter
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
Clock cycle time
CL=3
CL=2.5
CL=2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
Symbol Min Max Min Max Min Max Min Max Units
tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns
tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
tCK (3) 5
7.5
ns
tCK (2.5) 6
13
6
13 7.5 13 7.5 13 ns
tCK (2) 7.5 13 7.5 13 7.5 13 10 13 ns
tDH 0.40
0.45
0.5
0.5
ns
tDS 0.40
0.45
0.5
0.5
ns
tDIPW 1.75
1.75
1.75
1.75
ns
tDQSCK -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns
tDQSH 0.35
0.35
0.35
0.35
tCK
tDQSL 0.35
0.35
0.35
0.35
tCK
tDQSQ
0.40
0.45
0.5
0.5 ns
tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tCK
tDSS 0.2
0.2
0.2
0.2
tCK
tDSH 0.2
0.2
0.2
0.2
tCK
tHP tCH, tCL
tCH, tCL
tCH, tCL
tCH, tCL
ns
tHZ
+0.70
+0.70
+0.75
+0.75 ns
tLZ -0.70
-0.70
-0.75
-0.75
ns
tIHf 0.60
0.75
0.90
0.90
ns
tISf 0.60
0.75
0.90
0.90
ns
tIHs 0.60
0.80
1
1
ns
tISs 0.60
0.80
1
1
ns
tIPW 2.2
2.2
2.2
2.2
ns
tMRD
10
12
15
15
ns
tQH tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
ns
tQHS
0.50
0.55
0.75
0.75 ns
tRAS 40 70,000 42 70,000 40 120,000 45 120,000 ns
tRAP
15
15
15
20
ns
tRC
55
60
60
65
ns
tRFC
70
72
75
75
ns
Notes
16
16
22
22
22
14,17
14,17
17
13,14
18
8,19
8,20
6
6
6
6
13,14
15
21
June 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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