LPC1767 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
LPC1767 Datasheet PDF : 79 Pages
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NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Table 3. Pin allocation table …continued
Pin Symbol
Pin Symbol
Row J
1 P0[28]/SCL0/
USB_SCL
2 P0[27]/SDA0/
USB_SDA
5 P1[22]/MCOB0/
USB_PWRD/
MAT1[0]
9 P2[13]/EINT3/
I2STX_SDA
Row K
1 P3[26]/STCLK/
MAT0[1]/PWM1[3]
5 P1[23]/MCI1/
PWM1[4]/MISO0
6 VSS
10 P2[10]/EINT0/NMI
2 VDD(3V3)
6 P1[26]/MCOB1/
PWM1[6]/CAP0[0]
9 P0[11]/RXD2/
SCL2/MAT3[1]
10 P2[12]/EINT2/
I2STX_WS
Pin Symbol
3 P0[29]/USB_D+
7 P1[28]/MCOA2/
PCAP1[0]/
MAT0[0]
11 -
3 VSS
7 P1[27]/CLKOUT
/USB_OVRCR/
CAP0[1]
11 -
Pin Symbol
4 P1[19]/MCOA0/
USB_PPWR/
CAP1[1]
8 P0[1]/TD1/RXD3/SCL1
12 -
4 P1[20]/MCI0/
PWM1[2]/SCK0
8 P0[0]/RD1/TXD3/SDA1
12 -
6.2 Pin description
Table 4. Pin description
Symbol
Pin
Ball
P0[0] to P0[31]
P0[0]/RD1/TXD3/ 46[1]
SDA1
K8[1]
P0[1]/TD1/RXD3/ 47[1]
SCL1
J8[1]
P0[2]/TXD0/AD0[7] 98[2]
C4[2]
P0[3]/RXD0/AD0[6] 99[2]
A2[2]
Type
I/O
I/O
I
O
I/O
I/O
O
I
I/O
I/O
O
I
I/O
I
I
Description
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 0 pins depends upon the pin function
selected via the pin connect block. Pins 12, 13, 14, and 31 of this port
are not available.
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only).
TXD3 — Transmitter output for UART3.
SDA1 — I2C1 data input/output. (This is not an I2C-bus compliant
open-drain pin).
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only).
RXD3 — Receiver input for UART3.
SCL1 — I2C1 clock input/output. (This is not an I2C-bus compliant
open-drain pin).
P0[2] — General purpose digital input/output pin.
TXD0 — Transmitter output for UART0.
AD0[7] — A/D converter 0, input 7.
P0[3] — General purpose digital input/output pin.
RXD0 — Receiver input for UART0.
AD0[6] — A/D converter 0, input 6.
LPC1769_68_67_66_65_64_63
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 5 April 2011
© NXP B.V. 2011. All rights reserved.
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