25AA1024 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

25AA1024

1 Mbit SPI Bus Serial EEPROM

Microchip Technology 

25AA1024/25LC1024

2.8 PAGE ERASE

The Page Erase function will erase all bits (FFh) inside

the given page. A Write Enable (WREN) instruction

must be given prior to attempting a Page Erase. This

is done by setting CS low and then clocking out the

proper instruction into the 25XX1024. After all eight

bits of the instruction are transmitted, the CS must be

brought high to set the write enable latch.

The Page Erase function is entered by driving CS low,

followed by the instruction code (Figure 2-8), and

three address bytes. Any address inside the page to

be erased is a valid address.

FIGURE 2-8:

PAGE ERASE SEQUENCE

CS must then be driven high after the last bit if the

address or the Page Erase will not execute. Once the

CS is driven high, the self-timed Page Erase cycle is

started. The WIP bit in the STATUS register can be

read to determine when the Page Erase cycle is

complete.

If a Page Erase function is given to an address that

has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

CS

SCK

SI

0 1 2 3 4 5 6 7 8 9 10 11

29 30 31

Instruction

24-bit Address

0 1 0 0 0 0 1 0 23 22 21 20

210

High-Impedance

SO

DS21836D-page 14

Preliminary

© 2007 Microchip Technology Inc.

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