NM25C160 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
Manufacturer
NM25C160
Fairchild Semiconductor
NM25C160 Datasheet PDF : 10 Pages
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Functional Description (Continued)
READ SEQUENCE: Reading the memory via the serial SPI link TABLE 3. Block Write Protection Levels
requires the following sequence. The CS line is pulled low to select
the device. The READ op-code is transmitted on the SI line
followed by the high order address byte (A10–A8), and the low
order address byte (A7–A0). The leading three bits in the high
order address byte will be ignored. After this is done, data on the
Level
0
Status Register Bits
BP1
0
BP0
0
Array
Address
Protected
None
SI line becomes don’t care. The data (D7–D0) at the address
1
0
1
600-7FF
specified is then shifted out on the SO line. If only one byte is to
be read, the CS line can be pulled back to the high level. It is
2
1
0
400-7FF
possible to continue the READ sequence as the byte adress is
3
1
1
000-7FF
automatically incremented and data will continue to be shifted out.
When the highest address is reached (7FF), the address counter
rolls over to lowest address (000) allowing the entire memory to be
read in one continuous READ cycle. See Figure 6.
WRITE ENABLE (WREN): When VCC is applied to the chip, it
“powers up” in the write disable state. Therefore, all programming
modes must be preceded by a WRITE ENABLE (WREN) instruc-
FIGURE 6. Read Sequence
CS
Read Byte H Byte L
SI
Op-Code Addr. n Addr. n
tion. At the completion of a WRITE or WRSR cycle the device is
automatically returned to the write disable state. Note that a
WRITE DISABLE (WRDI) instruction will also return the device to
the write disable state. See Figure 8.
FIGURE 8. Write Enable
CS
SO
Data Data Data Data
n n+1 n+2 n+3
SI
DS012402-8
READ STATUS REGISTER (RDSR) : The Read Status Register
SO
WREN Op-Code
(RDSR) instruction provides access to the status register is used
DS012402-10
to interrogate the READY/BUSY and WRITE ENABLE status of WRITE DISABLE (WRDI): To protect against accidental data
the chip. Two non-volatile status register bits are used to select disturbance the WRITE DISABLE (WRDI) instruction disables all
one of four levels of BLOCK WRITE PROTECTION. The status programming modes. See Figure 9.
register format is shown in Table 2.
TABLE 2. Status Register Format
Bit Bit Bit Bit Bit Bit Bit Bit
7
65
43
210
X
X
X
X BP1 BP0 WEN RDY
X = Don't Care
Status register Bit 0 = 0 (RDY) indicates that the device is READY;
Bit 0 = 1 indicates that a program cycle is in progress. Bit 1 = 0
(WEN) indicates that the device is not WRITE ENABLED; Bit 1 =
FIGURE 9. Write Disable
CS
SI
WRDI Op-Code
SO
DS012402-11
1 indicates that the device is WRITE ENABLED. Non-volatile
status register Bits 2 and 3 (BP0 and BP1) indicate the level of
BLOCK WRITE PROTECTION selected. The block write protec- WRITE SEQUENCE: To program the device, the WRITE PRO-
tion levels and corresponding status register control bits are TECT (WP) pin must be held high and two separate instructions
shown in Table 3. Note that if a RDSR instruction is executed must be executed. The chip must first be write enabled via the
during a programming cycle only the RDY bit is valid. All WRITE ENABLE instruction and then a WRITE instruction must
other bits are 1s. See Figure 7.
be executed. Moreover, the address of the memory location(s) to
be programmed must be outside the protected address field
FIGURE 7. Read Status
CS
RDSR
SI
Op-Code
SO
SR Data
MSB…LSB
selected by the Block Write Protection Level. See Table 3.
DS012402-9
NM25C160 Rev. D.1
7
www.fairchildsemi.com
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