C32025 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
C32025 Datasheet PDF : 9 Pages
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Pin Description
Name
clk
Type
I
Polarity/
Bus size
Rise
clkout1
O
-
clkout2
O
-
rs_n
I
Low
mpmc
I
-
sync_n
I
Fall
hold_n
I
Low
holda_n
O
Low
int0_n
I
Low/Fall
int1_n
I
Low/Fall
int2_n
I
Low/Fall
iack_n
I
Low
ps_o
ds_o
is_o
ps_tri
ds_tri
is_tri
rw_o
O
Low
O
Low
O
Low
O
High
O
High
O
High
O
-
rw_tri
O
H
strb_o
O
Low
strb_tri
O
High
ready
I
High
bio_n
br_n
I
Low
O
Low
C32025 Megafunction Datasheet
Description
Master clock input
All internal synchronous circuits clock
Master clock output (fclk/4)
When High it indicates internal quarter-phases Q3 and Q4
Second clock output (fclk/4)
When High it indicates internal quarter-phases Q2 and Q3
Hardware reset input
Active for 2 cycles resets the device
Microprocessor/microcomputer mode
When Low the internal ROM is mapped into program space
Synchronization input
Forces the internal quarter-phase to Q1
Hold input
Forces processor to place the data & address buses and control lines
in the hi-Z state
Hold acknowledge output
Indicates that processor is in the hold mode
External interrupt inputs
External interrupt 0
External interrupt 1
External interrupt 2
Interrupt acknowledge
Indicates branching to the interrupt vector
Program, data and I/O space select signals
Select signals tri-state control
Enables external tri-state buffers
Read/write output signal
Indicates external transfer direction. High means reading
Read/write tri-state control
Enables external tri-state buffer
Strobe signal
Low indicates an external bus cycle
Strobe tri-state control signal
Enables external tri-state buffer
Data ready input
Indicates that external device is prepared for transfer to be
completed
Branch control input
When active the BIOZ branch occurs
Bus request output
Asserted when the processor requires access to external global data
memory space
CAST, Inc.
May 2004
Page 3
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