C32025 View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

C32025

Digital Signal Processor Megafunction

Unspecified 

C32025 Megafunction Datasheet

Functional Description

The C32025 core is partitioned into modules as described below.

Control Unit

Control unit consists of Program Counter (PC) and Prefetch Counter (PFC) used for program addressing and

pipelining. Sequencer is responsible for data flow organization. Repeat Counter (RPTC) is used to repeat the

execution of several instructions, especially data-intensive ones.

Memory Control Unit

It is an interface between the processor and all on-chip or off-chip memories. There are three internal RAM

blocks interfaces, internal ROM interface and external address and data buses. External wait states are

possible.

Central Arithmetic Logic Unit

Central Arithmetic-Logic Unit. (CALU) performs:

• Sign-extended shifting

• 32-bit arithmetic operations

• 32-bit logic operations

• 16-bit signed or unsigned multiplication

Auxiliary Registers Unit

Eight auxiliary registers are used for indirect data addressing or temporary data storage. Auxiliary Registers

Arithmetic Unit performs operations on current auxiliary register after each indirect data memory read/write.

Stack Unit

Eight level hardware stack for PC storage during subroutine calls and interrupt service.

Peripherals

There is one 16-bit continuously operating timer with programmable period. Synchronous full-duplex serial

interface can be used for interfacing serial AD/DA converters and codecs.

Interrupt Controller

There are three external interrupts, both edge and level triggered. Internal interrupt is generated at timer

underflow or serial port transmit/receive completion. Those six interrupts are maskable using Interrupt Mask

Register (IMR). There is also one non-maskable software interrupt.

CAST, Inc.

Page 6

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