C32025 Megafunction Datasheet
Verification Methods
The C32025 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus
was applied to a hardware model that contained the original Texas Instruments TMS320C25 chip, and the
results compared with the core’s simulation outputs.
Development Environment
• VHDL source code for the C32025
• Synthesis support - Complete set of synthesis scripts for Synopsys
• Simulation support – A set of scripts and macros for Synopsys, MTI, and Aldec
• Example CHIP_C32025 – TMS320C25 compatible design
This design uses the C32025 and illustrates how to build and connect memories and tri-state buffers
• Extensive HDL Test Bench that instantiates:
o Example design CHIP_C32025
o External RAM
o External ROM
o External I/O
o Clock generator
o Process that compares your simulation results with the expected results
• A collection of test assembler programs which are executed directly by the Test Bench
• A set of expected results
• Additional documentation
o Architectural overview
o Hardware description
o User Guide
o Design support including consulting
CAST, Inc.
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