MT48LC128M4A2A2TG-75 View Datasheet(PDF) - Micron Technology
Part Name
Description
Manufacturer
MT48LC128M4A2A2TG-75 Datasheet PDF : 55 Pages
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Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
12 11 10 9 8 7
Reserved* WB Op Mode
6 543
CAS Latency BT
2 10
Burst Length
Mode Register (Mx)
*Should program
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined Standard Operation
-
-
-
All other states reserved
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
Figure 1
Mode Register Definition
ADVANCE
512Mb: x4, x8, x16
SDRAM
Table 1
Burst Definition
Burst
Length
2
4
8
Full
Page
(y)
Starting Column Order of Accesses Within a Burst
Address Type = Sequential Type = Interleaved
A0
0
0-1
1
1-0
A1 A0
00
0-1-2-3
01
1-2-3-0
10
2-3-0-1
11
3-0-1-2
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0
0 1 0 2-3-4-5-6-7-0-1
0 1 1 3-4-5-6-7-0-1-2
1 0 0 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4
1 1 0 6-7-0-1-2-3-4-5
1 1 1 7-0-1-2-3-4-5-6
n = A0-A11/9/8 Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
(location 0-y)
…Cn - 1,
Cn…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTE: 1. For full-page accesses: y = 4,096 (x4); y = 2,048
(x8); y = 1,024 (x16).
2. For a burst length of two, A1-A9, A11, A12 (x4);
A1-A9, A11 (x8); or A1-A9 (x16) select the block-
of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four, A2-A9, A11, A12 (x4);
A2-A9, A11 (x8); or A2-A9 (x16) select the block-
of-four burst; A0-A1 select the starting column
within the block.
4. For a burst length of eight, A3-A9, A11, A12 (x4);
A3-A9, A11 (x8); or A3-A9 (x16) select the block-
of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and
A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9
(x16) select the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9, A11, A12 (x4);
A0-A9, A11 (x8); or A0-A9 (x16) select the unique
column to be accessed, and Mode Register bit M3
is ignored.
512Mb: x4, x8, x16 SDRAM
512MSDRAM_D.p65 – Rev. D; Pub 1/02
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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