CS48DV2B View Datasheet(PDF) - Cirrus Logic
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Description
Manufacturer
CS48DV2B Datasheet PDF : 26 Pages
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CS48DV2B Data Sheet
32-bit Audio DSP for Dedicated Dolby Volume and Audistry by Dolby
5.10 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1
SCP_CS falling to SCP_CLK rising 3
Symbol Min
fspisck
-
tspicss
-
Typical
11*DCLKP +
(SCP_CLK PERIOD)/2
Max
Fxtal/22
-
Units
MHz
ns
SCP_CLK low time
tspickl
20
-
ns
SCP_CLK high time
tspickh
20
-
ns
Setup time SCP_MISO input
tspidsu
9
-
ns
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
T SCP_CLK low to SCP_CS falling
F SCP_CLK low to SCP_CS rising
tspidh
5
tspidov
-
tspicsl
7
tspicsh
-
11*DCLKP +
(SCP_CLK PERIOD)/2
-
ns
8
ns
-
ns
-
ns
A Bus free time between active SCP_CS
tspicsx
SCP_CLK falling to SCP_MOSI output high-Z
tspidz
-
3*DCLKP
-
ns
20
ns
R 1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
D maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.7.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter
IAL HI tspicss
T P EE_CS#
N L tspicsl
tspickl
0
1
2
6
7
0
5
E E SCP_CLK
fspisck
tspickh
ID D SCP_MISO
F SCP_MOSI
A6
tspidsu
A5
tspidh
A0 R/W MSB
tspidov
MSB
tspicsx
6
7
tspicsh
LSB
LSB
tspidz
CONFigure 4. Serial Control Port - SPI Master Mode Timing
DS875F2
Copyright 2009 Cirrus Logic
15
CONFIDENTIAL
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