CY7C1069AV33-8ZI View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
CY7C1069AV33-8ZI Datasheet PDF : 9 Pages
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CY7C1069AV33
AC Test Loads and Waveforms[3]
OUTPUT
Z0= 50Ω
50Ω
30 pF*
VTH = 1.5V
(a)
*Capacitive Load consists of all
3.3V
components of the test environment
GND
Rise time > 1V/ns
All input pulses
90%
10%
(c)
3.3V
R1 317 Ω
OUTPUT
5 pF*
90%
10% (b)
R2
351Ω
*Including
jig and
scope
Fall time:
> 1V/ns
AC Switching Characteristics Over the Operating Range [4]
–8
–10
–12
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tpower
VCC(typical) to the First Access[5]
1
tRC
Read Cycle Time
8
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
3
tACE
CE1 LOW/CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z[6]
1
tHZOE
OE HIGH to High-Z[6]
tLZCE
CE1 LOW/CE2 HIGH to Low-Z[6]
3
tHZCE
CE1 HIGH/CE2 LOW to High-Z[6]
tPU
CE1 LOW/CE2 HIGH to Power-up[7]
0
tPD
CE1 HIGH/CE2 LOW to Power-down[7]
Write Cycle[8, 9]
1
1
ms
10
12
ns
10
10
12
ns
3
3
ns
8
10
12
ns
5
5
6
ns
1
1
ns
5
5
6
ns
3
3
ns
5
5
6
ns
0
0
ns
8
10
12
ns
tWC
Write Cycle Time
8
10
12
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
6
7
8
ns
tAW
Address Set-up to Write End
6
7
8
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
6
7
8
ns
tSD
Data Set-up to Write End
5
5.5
6
ns
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[6]
WE LOW to High-Z[6]
0
0
0
ns
3
3
3
ns
5
5
6
ns
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD , normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation
is started.
6. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV
from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE1 LOW / CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of
the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05255 Rev. *D
Page 4 of 9
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