DSP56371 View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
Manufacturer
DSP56371
Freescale Semiconductor
DSP56371 Datasheet PDF : 124 Pages
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Signal/Connection Descriptions
3.3 Ground
Table 3. Grounds
Ground Name
Description
PLLA_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
PLLP_GND(1) ground. The user must provide adequate external decoupling capacitors.
PLLD_GND(1) PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
CORE_GND (4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND (5)
SHI, ESAI, ESAI_1, DAX and Timer I/O Ground—IO_GND is an isolated ground for the SHI,
ESAI, ESAI_1, DAX and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
3.4 SCAN
Signal
Name
SCAN
Type
Input
State
during
Reset
Input
Table 4. SCAN signals
Signal Description
SCAN—Manufacturing test pin. This pin should be pulled low.
Internal Pull down resistor.
3.5 Clock and PLL
Table 5. Clock and PLL Signals
Signal
Name
EXTAL
Type
Input
State
during
Reset
Input
Signal Description
External Clock Input—An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
PINIT/NMI Input
Input
This input cannot tolerate 5 V.
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is
a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
Internal Pull up resistor.
This input is 5 V tolerant.
3.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is
deasserted, these inputs are hardware interrupt request lines.
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DSP56371 Technical Data
Freescale Semiconductor
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