DSP56371 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

DSP56371

high density CMOS device with 5.0-volt compatible inputs and outputs.

Freescale Semiconductor 

DSP56371 Overview

5

2

12

12

11

Memory Expansion Area

SHI

Interface

Triple

Timer

ESAI ESAI_1

Interface Interface

GPIO

EFCOP

Program

RAM

4K × 24

X Data

RAM

36K × 24

Y Data

RAM

48K × 24

2

DAX

Address

Generation

Unit

Six Channel

DMA Unit

Bootstrap

ROM

Internal

Data

Bus

Switch

Peripheral

Expansion Area

ROM

64K × 24

ROM

32K × 24

ROM

32K × 24

YAB

XAB

PAB

DAB

24-Bit

DSP56300

Core

DDB

YDB

XDB

PDB

GDB

Clock

Gen-

erator

PLL

Program

Interrupt

Controller

Program

Decode

Controller

Power

Mngmnt.

Program

Data ALU

4

JTAG

Address

Generator

24 × 24+56→56-bit MAC

Two 56-bit Accumulators

OnCE™

56-bit Barrel Shifter

EXTAL

RESET

PINIT/NMI

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

Figure 1. DSP56371 Block Diagram

2.2 DSP56300 Core Description

The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice

the performance of Motorola's popular DSP56000 core family while retaining code compatibility with it.

The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low

power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products. For a description

of the DSP56300 core, see Section 2.4 DSP56300 Core Functional Blocks. Significant architectural enhancements to the

DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA).

The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library

of standard predesigned elements such as memories and peripherals. New modules may be added to the library to meet

customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a

wide variety of memory and peripheral configurations. Refer to DSP56371 User Manual, Section 3, Memory Configuration.

Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral features are described in this

manual.

2

DSP56371 Technical Data

Freescale Semiconductor

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