ES6028 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
ES6028 Datasheet PDF : 10 Pages
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ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
Table 1 ES6028 Pin Description (Continued)
Name
Pin Numbers
I/O
TSD0
SEL_PLL0
O
33
I
TSD1
SEL_PLL1
O
36
I
TSD2
37
O
NC
38, 42, 48
—
MCLK
39
I/O
TBCK
40
I/O
SPDIF
O
I
Definition
Audio transmit serial data output 0.
Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data output 1.
Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data output 2.
No connect pins. Leave open.
Audio master clock for audio DAC.
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
S/PDIF output.
Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
SEL_PLL3
41
SEL_PLL3 Clock Source
0
Crystal oscillator
1
DCLK input
RSD
RWS
RBCK
XIN
XOUT
AVEE
AVSS
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
DB[15:0]
DCS[1:0]#
DQM
DSCK
45
I Audio receive serial data.
46
I Audio receive frame sync.
47
I Audio receive bit clock.
49
I 27-MHz crystal input.
50
O 27-MHz crystal output.
51
P Analog power for PLL.
52
G Analog ground for PLL.
53-58, 61-66
O DRAM address bus.
69
O DRAM column address strobe.
O DRAM output enable.
70
O DRAM clock enable.
71
O DRAM write enable.
72
O DRAM row address strobe.
73
O SDRAM bank select 0.
74
O SDRAM bank select 1.
77-82, 85-90, 93-96 I/O DRAM data bus.
97,100
O SDRAM chip select.
101
O Data input/output mask.
102
O Output clock to SDRAM.
4
SAM0462-031704
ESS Technology, Inc.
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