HB28E016BP2 View Datasheet(PDF) - Hitachi -> Renesas Electronics

Part Name

Description

Manufacturer

HB28E016BP2

Mobile Embedded Flash with MultiMediaCard™ Interface 16 Mbyte/32 Mbyte

Hitachi -> Renesas Electronics 

HB28E016/D032BP2

Block Diagram

C7 E8 A9 D10 D5 D3 F6

VPP CS CMD/DI

Generator

VCC

CLK/SCLK DAT/DO

Interface driver

Internal clock

OCR[31:0]

CID[127:0]

CSD[127:0]

RCA[15:0]

Interface

Flash control

Core control

Memory core

All units in these Hitachi Mobile Embedded Flashes are clocked by an internal clock generator. The

Interface driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock

signal. The card is controlled by the three line MultiMediaCard interface containing the signals: CMD,

CLK, DAT (refer to Chapter “Interfaces”). For the identification of these Hitachi Mobile Embedded

Flashes in a stack of Hitachi Mobile Embedded Flashes, a card identification register (CID) and a relative

card address register (RCA) is foreseen. An additional register contains different types of operation

parameters. This register is called card specific data register (CSD). The communication using the

MultiMediaCard lines to access either the memory field or the registers is defined by the MultiMediaCard

standard (refer to Chapter “Communication”). The card has its own power on detection unit. No additional

master reset signal is required to setup the card after power on. It is protected against short circuit during

insertion and removal while the MultiMediaCard system is powered up (refer to Chapter “Power Supply”).

No external programming voltage supply is required. The programming voltage is generated on card.

These Hitachi Mobile Embedded Flashes support a second interface operation mode the SPI interface

mode. The SPI mode is activated if the CS signal is asserted (negative) during the reception of the reset

command (CMD0) (refer to Chapter “SPI Communication”).

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